Short-channel MOSFETs Research Articles

Characterization and modelling of MOSFET operating at cryogenic temperature for hybrid superconductor-CMOS circuits

Short channel MOSFET devices have been fabricated using a commercial 0.25 µm CMOS process and characterized at cryogenic temperatures for further application in hybrid superconductor-CMOS circuits. A 4 K device model has been established through modifying the room temperature CMOS model by taking into account the parameter variation of the discrete MOS devices at cryogenic temperature. We have demonstrated that the circuit simulation based on this model is comparable with the measurement at 4 K on a 31-stage ring oscillator both with and without long wire interconnect; therefore, the cryogenic model is acceptable for circuit simulation. Circuit performance at cryogenic temperature has been studied by a set of ring oscillator experiments and a 60–70% improvement of the propagation delay of MOS device and circuit with interconnect wire at 4 K has been reported.

Drain current thermal noise modeling for deep submicron n- and p-channel MOSFETs

The drain current thermal noise has been measured and modeled for the short-channel devices fabricated with a standard 0.18 μm CMOS technology. We have derived a physics-based drain current thermal noise model for short-channel MOSFETs, which takes into account the velocity saturation effect and the carrier heating effect in gradual channel region. As a result, it is found that the well-known Qinv/L2––formula, previously derived for long-channel, remains valid for even short-channel. The model excellently explained the carefully measured drain thermal noise for the entire VGS and VDS bias regions, not only in the n-channel, but also in the p-channel MOSFETs. Large excess noise, which was reported earlier in some other groups, was not observed in both the n-channel and the p-channel devices.

Fabrication of 50 nm Trigate Silicon On Insulator Metal–Oxide–Silicon Field-Effect Transistor without Source/Drain Activation Annealing

This paper presents the electrical characteristics of trigate silicon-on-insulator (SOI) n-type metal–oxide–silicon field-effect transistor (n-MOSFET) devices with a gate length of 50 nm, a channel width of 100 nm, and a channel thickness of 30 nm. The source and drain of these trigate SOI n-MOSFETs were formed by ion-shower doping at 250°C. In particular, activation annealing after ion-shower doping was excluded in order to improve the lateral steepness of the source/drain junction. Without any additional thermal processes, a low sheet resistance (Rs) of 1.2 kΩ/□ was obtained by ion-shower doping, and trigate MOSFETs showed satisfactory electrical characteristics. Since the short-channel effect was suppressed and the ratio of maximum drain current to minimum drain current (Imax/Imin) as ∼105, it is thought that the ion-shower doping process is effective for fabricating short-channel trigate SOI MOSFET devices.

Electrical analysis of external mechanical stress effects in short channel MOSFETs on (0 0 1) silicon

This paper presents an electrical analysis of external mechanical stress effects on devices characteristics for long and short channel MOSFETs in advanced 0.13 μm technology. Similar bulk and SOI generations for nMOS and pMOS devices are studied. By applying external calibrated stress we measure piezoresistive effects and compare small and long transistors electrical responses. Main results are that the threshold voltage ( V t) variations were shown negligible whereas mobility dependence with stress was the most significant effect. After the parasitic series resistance ( R sd) correction on short devices, we extracted comparable piezoresistive coefficients on short and long devices indicating that 2D or local effects can be neglected in all cases. Comparison bulk/SOI showed slightly higher piezoresistive coefficients for SOI. Finally, measurement errors were estimated.

Buffer delay change in the presence of power and ground noise

Variations of power and ground levels affect very large scale integration circuit performance. Trends in device technology and in packaging have necessitated a revision in conventional delay models. In particular, simple scalable models are needed to predict delays in the presence of uncorrelated power and ground noise. In this paper, we analyze the effect of such noise-on-signal propagation through a buffer and present simple, closed-form formulas to estimate the corresponding change of delay. The model captures both positive (slowdown) and negative (speedup) delay changes. It is consistent with short-channel MOSFET behavior, including carrier velocity saturation effects. An application shows that repeater chains using buffers instead of inherently faster inverters tend to have superior supply-level-induced jitter characteristics. The expressions can be used in any existing circuit performance optimization design flow or can be combined into any delay calculations as a correction factor.

Technology for nanoperiodic doping of a metal–oxide–semiconductor field-effecttransistor channel using a self-forming wave-ordered structure

A self-forming nanostructure—a wave-ordered structure with a controllableperiod (20–180 nm)—results from the off-normal bombardment ofamorphous silicon layers by low-energy (∼ 1–10 keV)nitrogen ions. The nanostructure has been modified by reactive-ion etching inplasma to form a periodic nanomask on the surface of the channel region of ametal–oxide–semiconductor field-effect transistor (MOSFET). Implantation ofarsenic ions through the nanomask followed by the technological stepscompleting the fabrication of the MOSFET resulted in a periodically dopedchannel field-effect transistor (PDCFET), which can be considered as achain of short-channel MOSFETs with a common gate. Having worsesubthreshold characteristics, PDCFETs show greater drain current andtransconductance than to MOSFETs without a periodically doped channel. Thisimprovement in device performance is attributed to the fact that thechannel length is cut by the length of high-conductivity doped areas in thechannel and that the voltage is distributed between the areas, depressing thescaling rules for short-channel MOSFETs and allowing the channel tobe less doped between the areas, thus keeping drift mobility high.

Short-channel single-gate soi mosfet model

The authors derive an analytical model for threshold voltage for fully depleted single-gate silicon-on-insulator (SOI) MOSFETs taking into consideration the two-dimensional effects in both SOI and buried-oxide layers. Their model is valid for both long- and short-channel SOI MOSFETs and demonstrates the dependence of short-channel effects on the device parameters of channel-doping concentration, gate oxide, SOI, and buried-oxide thickness. It reproduces the numerical data for sub-0.1-/spl mu/m gate-length devices better than previous models.

Noise modeling for RF CMOS circuit simulation

The RF noise in 0.18-/spl mu/m CMOS technology has been measured and modeled. In contrast to some other groups, we find only a moderate enhancement of the drain current noise for short-channel MOSFETs. The gate current noise on the other hand is more significantly enhanced, which is explained by the effects of the gate resistance. The experimental results are modeled with a nonquasi-static RF model, based on channel segmentation, which is capable of predicting both drain and gate current noise accurately. Experimental evidence is shown for two additional noise mechanisms: 1) avalanche noise associated with the avalanche current from drain to bulk and 2) shot noise in the direct-tunneling gate leakage current. Additionally, we show low-frequency noise measurements, which strongly point toward an explanation of the 1/f noise based on carrier trapping, not only in n-channel MOSFETs, but also in p-channel MOSFETs.

A new drain current model for short-channel MOSFETs

Reduction of channel length makes the channel current to be less than that of drain current. In this paper, by using multiplication factor model [Proc. IEEE IRPS. (1996) 318, Proc. IEEE IRPS (1999) 167] and a simple approximation of the collector current of PBT the drain current in short-channel MOSFETs is modeled and simulated. This model makes use of four parameters, which by extracting them for each device, it is possible to calculate total drain current. The simulation results from this model are compared with the results obtained from MINIMOS, in which match observed between them.

A technique for dynamic CMOS noise immunity evaluation

While dynamic CMOS logic is considered an attractive circuit technique, it suffers from noise problems. Noise may affect dynamic CMOS circuits in many ways. In this paper, new models have been developed that consider a noise pulse on one of the circuit inputs or on the clock input. These models specify the circuit noise immunity in terms of both the amplitude and the duration of a noise pulse. HSPICE simulations confirm the validity of these models for both long and short-channel MOSFETs. As dynamic circuits are designed around the constraint of noise, the models presented here clearly indicate parameters that affect noise and their influence, and how it could aid digital circuit designs.

Phonon assisted tunneling in gated p-i-n diodes

Recently it was shown that transistors based on vertical gated p-i-n diodes can be fabricated by Molecular Beam Epitaxy (MBE). At a very low supply voltage of −0.2 V, a current gain up to five orders of magnitude with saturation behavior is achieved. Supported by simulations, we discuss in the present article the electronic transport from transistor source to drain in the influenced two-dimensional electron channel as a function of doping profiles, oxide thickness, supply and gate voltage. Experimental data of devices, manufactured by means of MBE, indicate that the electron transport is ruled by a gate-controlled Esaki like phonon assisted tunneling mechanism. The results further show the possibility of scaling down such devices into the dimensions range of short channel MOSFETs for future Complementary Metal Oxide Semiconductor (CMOS) applications. Taking all the results into account, we discuss an advanced, completely new device similar to the fully-depleted double-gate MOSFET.

Effect of mechanical stress induced by etch-stop nitride: impact on deep-submicron transistor performance

This paper reports that process-induced mechanical stress affects the performance of short-channel MOSFETs, and focuses on the effect of a plasma-enhanced CVD nitride contact-etch-stop layer. The stress in the channel region induced by the nitride layer changes transconductance ( G m), thereby changing the device performance. When the nitride stress varies from +300 MPa (tensile) to −1.4 GPa (compressive), NMOSFET performance degrades by up to 8% and PMOSFET performance improves up to 7%. These changes are caused by the modulation of the electron/hole mobilities, so controlling process-induced stress and considering this mobility change in a precise transistor model are necessary for deep-submicron transistor design.

A simple subthreshold swing model for short channel MOSFETs

A new approach to calculate the subthreshold swing of short channel bulk and silicon-on-insulator metal oxide semiconductor field effect transistors is presented. The procedure utilizes a channel-potential expression appropriate for submicron dimensions. The final result is similar to that used for long channels except for a factor λ which represents the short channel effects. Comparison with different published results reveals excellent quantitative agreement.

Physical origin of the excess thermal noise in short channel MOSFETs

The physical origin of the excess thermal noise in short channel MOSFETs is explained based on numerical noise simulation. The impedance field representation and extraction method demonstrate that the drain current noise is dominated by source side contributions. Analysis identifies local ac channel resistance variations as the primary controlling factor. The nonlocal nature of velocity results in a smaller derivative of the velocity with respect to the field which in turn causes a higher local ac resistance near the source junction.

High frequency thermal noise modelling of short-channel MOSFET's

A complete treatment of the thermal noise in a MOSFET including both drain current noise and induced gate current noise has been developed by deriving a small-signal model valid at high frequencies and for short-channel devices. On the basis of this model the parameters currently used for the representation of a noisy two-port have been derived. As those parameters depend on the noise sources and on the admittance matrix terms, both these contributions have been accurately modeled. Finally, the model has been applied to the derivation of MOSFET two-port noise parameters in order to minimize noise figure of low noise amplifiers.

A Physical Model for MOSFET Drain Current in Non-ohmic Regime Using Ohmic Regime Operation

In order to characterise the velocity saturation phenomena in short channel MOSFET's, a simple method is proposed in this work. It is based on the comparison between transistor behaviour in ohmic and saturation regime respectively. Therefore, the MOSFET characteristicId0(Vd). avoiding velocity saturation phenomena, can be obtained from ohmic characteristicId(Vg)and compared with the experimental characteristicId(Vd).

Characterization of Series Resistances and Mobility Attenuation Phenomena in Short Channel MOS Transistors

As the scaling proceeds, the transverse electric field increase, and a mobility attenuation phenomenon becomes of primordial interest. Indeed, the high transverse electric field is generally ascribed [1] to surface roughness scattering in the channel and consequently reduce effective mobility of carriers. In short channel MOSFET, the Source-Drain resistance Rsd influence strongly the effective mobility.The aim of this work is therefore to propose an original method especially conceived for the extraction of the series resistance Rsd. Using the approach of the Surface Roughness Scattering which enables a consistent modelling of the mobility to be obtained from low to high electric field [2], this allow to determine all model parameters in particular a Series Resistance from the plot of the transfer characteristic drain current Idversus gate voltage Vg Curves.

An Accurate Method for Extracting the Critical Field in Short Channel NMOS Devices

In this letter, an accurate method for extracting the critical fieldEcin short channel MOSFET's is presented. The principle of this method is based on the comparison between two models which give drain saturation voltage evolution against gate voltageVdsat(Vg)continuously. The results obtained by this technique have shown better agreement with measurements data and have allow in the same time to determine the validity domain of Sodini's law [1].

Piezoresistive characteristics of short-channel MOSFETs on (100) silicon

This paper demonstrates that the intrinsic piezoresistive response of the MOSFET channel is independent of length. The reported fall-off of the piezoresistive response of the transistor in short channel devices is shown to be the result of parasitic series resistance in the source of the transistor. At the same time, the experimental results demonstrate that the threshold voltage of the devices is essentially independent of stress. The results are verified for three independent processes.

Impact of the Stress on the Sub-Micron N-Metal Oxide Semiconductor Field Effect Transistor Characteristics

In this paper, we present a drain current model for stressed short-channel MOSFET's. Stress conditions are chosen so that the interface states generated by hot-carriers are dominant. The defects generated during stress time are simulated by a spatio-temporal gaussian distribution. The parasitic source and drain resistances are included. We also investigate the impact of the interface charge density, generated during stress, on the transconductance. Simulation results show a significant degradation of the drain current versus stress time.