Self-aligned Technique Research Articles

Nanodiamond Vacuum Field Emission Integrated Differential Amplifier

The development of a novel vacuum differential amplifier (diff-amp) array employing vertically configured nanodiamond (ND) vacuum field emission transistors (ND-VFETs) on a single chip is presented. The diff-amp array is composed of a common ND emitter array integrated with partition gates and split anodes. An identical pair of ND-VFETs with well-matched field emission transistor characteristics was fabricated by using a dual-mask well-controlled microfabrication process, involving a mold-transfer self-aligned gate-emitter technique in conjunction with ND deposition into the micropatterned molds in the active layer of a silicon-on-insulator substrate followed by gate partitioning to form diff-amp array. The ND-VFETs show gate-controlled modulation of emission with distinct cutoff, linear, and saturation regions. Signal amplification characteristics of the ND-VFET diff-amp are presented. A large common-mode-rejection ratio (CMRR) of 54.6 dB was measured for the diff-amp. The variation of CMRR performance with transconductance was examined, and the results were found to agree with the equivalent circuit model analysis. The accomplishment of this basic circuit building block, consisting of an integrated diff-amp, demonstrates the feasibility of using vacuum integrated circuits for practical applications, including high-radiation and temperature-tolerant space electronics.

Ultra-low Voltage, Self-aligned OTFTs for Frequency Applications

ABSTRACTA novel structure for Organic Thin-Film Transistor (OTFT) is here presented. The devices are fabricated using a one-mask, photolithographic self-alignment technique which can be performed with standard photoresists and without further chemical treatments. This technique, combined with a novel technology for the realization of low voltage OTFTs, allows a dramatic reduction of the parasitic capacitances thus leading to a remarkable cut-off frequency. In this paper, the main electrical parameters of low voltage, self-aligned devices are reported, and a complete frequency characterization of the devices is given. These characteristics make the reported approach suitable for the development of basic circuitries for frequency applications.

Towards high frequency performances of ultra-low voltage OTFTs: Combining self-alignment and hybrid, nanosized dielectrics

By combining an ultra-thin dielectric layer with a self-aligning process, an ultra-low voltage Organic Thin-Film Transistor (OTFT) with a 100kHz cutoff frequency was obtained. The devices are fabricated using a single-mask, photolithographic self-alignment technique compatible with the use of standard photoresists and not requiring any further chemical treatment. This technique allows a dramatic reduction of the parasitic capacitances thus leading to a remarkable increase of the cutoff frequency, even with organic semiconductors with a relatively low mobility. These characteristics make the reported approach suitable for the fabrication of basic building blocks for high frequency applications. In this paper, the main electrical parameters of ultra-low voltage, self-aligned devices are reported, and their complete frequency characterization is provided.

Ni80Fe20/Ni binary nanomagnets for logic applications

We demonstrate the functionality of Ni80Fe20/Ni binary nanostructures cells fabricated using self-aligned shadow deposition technique in logic applications. Depending on the magnetic ordering of the cells, distinct dynamic states probed by broadband ferromagnetic resonance spectroscopy are realized. We show that the magnetic ordering can be manipulated to achieve logic operations by controlling the amplitude and the orientation of reset fields. Magnetic force microscopy and micromagnetic simulations were used to validate our experimental results.

Flow profile measurement in microchannel using the optical feedback interferometry sensing technique

The need to accurately measure flow profiles in microfluidic channels is well recognised. In this work, we present a new optical feedback interferometry (OFI) flow sensor that accurately measures local velocity in fluids and enables reconstruction of a velocity profile inside a microchannel. OFI is a self-aligned interferometric technique that uses the laser as both the transmitter and the receiver thus offering high sensitivity, fast response, and a simple and compact optical design. The system described here is based on a commercial semiconductor laser and has been designed to achieve a micrometer-range spatial resolution. The sensor performance was validated by reconstructing the velocity profile inside a circular cross-section flow-channel with 320 $$\upmu $$ m internal diameter, with a relative error smaller than 1.8 %. The local flow velocity is directly measured, thus avoiding the need for model based profile calculation and uncertainties inherent to this approach. The system was validated by successfully extracting the flow profiles in both Newtonian and shear-thinning liquids.

Fabrication Issues of 4H-SiC Static Induction Transistors

The process technology for the fabrication of 4H-SiC Static Induction Transistors (SITs) has been developed. Conventional contact UV lithography and self-aligned techniques have been employed. Al-outdiffusion following Rapid Thermal Annealing (RTA) has been determined as the cause for the increased reverse leakage and early forward turn-on of the gate-source junction. The fabricated transistors, exhibited a specific RON value in the region of 2mΩ•cm2 and 80 V turn-off voltage.

THE DEVELOPMENT OF PERPENDICULAR MAGNETIC TUNNELING JUNCTIONS

This paper reviews the progress made over the last few years in understanding the development of perpendicular magnetic tunneling junctions (pMTJs). The material systems for making pMTJs, including rare-earth/transition metal alloys, L10-ordered (Co, Fe)–Pt alloys, Co/(Pd, Pt) multilayers, and CoFeB–MgO crystallized structures, are briefly introduced. The fabrication processes of the MTJ devices are focused on, consisting of open-trench, etch-back and self-aligned techniques. The authors also propose a spin-torque nano-oscillator based on pMTJ, for application in GHz range telecommunications.

Nickel Silicide Formation Using Excimer Laser Annealing

In this work, we report on a self-aligned nickel silicide formation technique based on excimer laser annealing (ELA). We evaluate this process for the front contact formation of industrial PERC type solar cells on random pyramid textured Si surfaces where damage to surface texture, emitter passivation, or to the shallow junction should be avoided or minimized. PERC type solar cells obtained by POCl3 diffusion were processed on large area (12.5x12.5cm2) CZ-Si. Self-aligned litho-free Ni/Cu contacts defined by ps-laser ablation of the SiO2/SiNx anti-reflective coating (ARC) and subsequent ELA of the Ni layer were compared to conventional Ag screen printed contacts.The novel ELA process results in an absolute gain in Jsc of 0.8mA/cm2 as well as a drop of 0.3Ω.cm2 in series resistance (Rs) compared to SP Ag contacts due to reduced shading and resistance losses. This leads to 0.5% absolute increase in efficiency from 19.3% to 19.7% since other characteristics (Voc, pFF) could be maintained to the same level. In this work, the best performing cell with the ELA process reached an outstanding 20.0% energy conversion efficiency with Jsc=39.3mA/cm2, Voc=649.8mV, and FF=78.3%.

Nitrogen-incorporated nanodiamond vacuum field emission transistor with vertically configured self-aligning gate

A vacuum field emission (VFE) transistor in vertical configuration with nitrogen-incorporated nanocrystalline-diamond emitters is presented. A novel self-aligned gate partition technique was utilized to construct the VFE device. The gate-controlled modulation of the emission current was demonstrated. A high emission current of 160μA and a low gate turn-on voltage of 25V were achieved. The device displayed high DC voltage gain of 1000 and negligible gate intercepted current, which are crucial features for microelectronic applications. Basic transistor characteristics with distinct cutoff, linear, and saturation regions were observed, revealing the practical application of the device for vacuum microelectronics and integrated circuits.

Self-alignment of RFID dies on four-pad patterns with water droplet for sparse self-assembly

This paper reports an in-depth study of a water-droplet-assisted self-alignment technique that self-aligns radio frequency identification (RFID) dies on four-pad patterns. The segmented structure of four hydrophilic pads on a hydrophobic substrate brings freedom to the design of the electrical functionality and the surface functionality. The paper investigates the influence of the key parameters that may affect the self-alignment in theory and experiment. The theoretical model justifies that RFID dies can be reliably aligned on the segmented four-pad pattern even when the initial placement error is as large as 50% of the size of the die and the gap between the four pads is about 10% of the size of the die. A method has been introduced to estimate the sufficient droplet volume for self-alignment. A series of experiments have been carried out to verify the results of the model. The experiments indicate that the self-alignment between the 730 × 730 µm RFID dies and the pattern occurs reliably when the releasing bias between the RFID die and antenna is less than 400 µm for patterns with 50 and 100 µm gaps, and successful self-alignment is possible even with greater bias of 500 µm.

Single-molecule sensing electrode embedded in-plane nanopore

Electrode-embedded nanopore is considered as a promising device structure for label-free single-molecule sequencing, the principle of which is based on nucleotide identification via transverse electron tunnelling current flowing through a DNA translocating through the pore. Yet, fabrication of a molecular-scale electrode-nanopore detector has been a formidable task that requires atomic-level alignment of a few nanometer sized pore and an electrode gap. Here, we report single-molecule detection using a nucleotide-sized sensing electrode embedded in-plane nanopore. We developed a self-alignment technique to form a nanopore-nanoelectrode solid-state device consisting of a sub-nanometer scale electrode gap in a 15 nm-sized SiO2 pore. We demonstrate single-molecule counting of nucleotide-sized metal-encapsulated fullerenes in a liquid using the electrode-integrated nanopore sensor. We also performed electrical identification of nucleobases in a DNA oligomer, thereby suggesting the potential use of this synthetic electrode-in-nanopore as a platform for electrical DNA sequencing.

Self-aligned reduction lithography using backside exposure through embedded masks

We demonstrate a novel self-aligned diffraction-based photolithographic technique, that uses embedded masks and backside exposure through transparent substrates, to fabricate sub-wavelength features with conventional photolithography tools. To demonstrate one potential application of this lithography tool, we produce arrays of metallic rings, split rings, and nanowires with feature sizes ranging from 130 nm and above, by modulating the exposure intensity, photoresist thickness, and etch time. The ability to produce both continuous and split rings composed of noble metals over wafer-sized areas has promise in low-cost techniques for fabricating metamaterials and other advanced optical devices.

Self-alignment in the stacking of microchips with mist-induced water droplets

This paper reports a novel and versatile water droplet self-alignment technique where the water is delivered in mist form onto the assembly site. The droplet forming process has been carefully investigated using machine vision, where each individual droplet on the microchip surface can be identified and the volume per surface area can be calibrated at a specific time. The result reveals that the volume of water droplets on the assembly surface grows linearly as a function of time. Self-alignment based on the mist-induced droplets has been studied, where a robotic microgripper is used to deliver the microchips on the assembly site. The paper also investigates the maximum tolerance of the initial placement error in stacking SU-8 chips 200 × 200 × 70 µm in size, and the possibility of stacking two SU-8 chips of different dimensions using the proposed self-alignment technique. Moreover, self-alignment of chips on hydrophilic/hydrophobic patterns covered by mist-induced water droplets has been studied. The experimental results indicate that this novel self-alignment technique is very promising. Furthermore, a statistical model has been used to validate the experimental results.

Micromachined thermoelectric IR sensors fabricated by a self-aligned process

In this paper, we report the fabrication and characterization of micromachinedthermoelectric IR sensors through a self-aligned technique. Unlike most conventionalfront-etched thermoelectric IR sensors, etching windows in the self-aligned process aredetermined by the spacing between polysilicon thermocouple legs. Due to etchingwindows for structure release being patterned by a self-aligned process ratherthan as a last photolithography step, the fabrication complication is reducedand narrow etching windows can be patterned. Using the self-aligned process,three types of thermoelectric IR sensors are fabricated and characterized. WithSiO2/Si3N4 as absorber layer, the sensor with rectangular structure shows the highest responsivity of43.5 V W − 1, and the circular-shaped sensor with polysilicon strips patterned in the absorber areashows the fastest response and the highest specific detectivity of . This self-aligned technique is also directly applicable to other MEMS devices withpolysilicon as the structure material, and also makes it possible to manufacture ultrasmallgaps.

High-Density Periodic Arrays of Self-Aligned Subwavelength Nanopyramids for Surface-Enhanced Raman Spectroscopy

Novel nanotextured surfaces are presented with periodically self-aligned subwavelength nanogroove and nanopyramid structures with precisely defined pitch lambda(g) that are closely packed with 2 nm separation gaps over large areas and form high-density arrays of hot-spot scattering sites ideally suited for surface-enhanced Raman scattering (SERS) and Raman spectroscopy. The simple self-aligning fabrication technique requires only a single lithography step and wet anisotropic etching. Measured average Raman enhancement factors of G approximate to 10(6) from rhodamine 60 (R6G) on patterned Au surfaces with lambda(g) = 200 nm are consistent with numerical calculations. The nanostructured surfaces can be scaled to smaller dimensions, which results in increased enhancement as well as increased hot-spot spatial density.

All inkjet-printed, fully self-aligned transistors for low-cost circuit applications

Layer-to-layer registration is a significant problem in printed electronics since parasitic overlap capacitances resulting from the poor registration of conventional printers substantially degrade device operating speeds. To overcome this, a novel inkjet printing process was utilized to demonstrate an all inkjet-printed and fully self-aligned transistor, as well as fully self-aligned inverters for the first time. Self-alignment of transistor source/drain electrodes to gates was achieved by a printed wetting-based roll-off process, resulting in an improved overlap capacitance as small as 0.14–0.23 pF mm −1. Circuit building blocks including transistor arrays and inverters were demonstrated using a novel self-split source/drain and a self-aligned interconnect printing technique. Due to the substantial reduction in overlap capacitance, demonstrated inverters showed a propagation delay as low as 0.488 ms at a fan-out of 1, despite using materials with mobility of 0.01 cm 2 V −1 s −1, thus showing a performance that is suitable for use in a range of low-cost electronics applications, realized using a simple, scalable process.

High-density Nano-scale N-channel Trench-gated MOSFETs Using the Self-aligned Technique

We propose a novel process technology for fabricating a very high density n-channel trench-gate metal oxide silicon field effect transistor (MOSFET) by using an oxide spacer and self-aligned techniques. Due to this nano-scale technology, the cell pitch of the trench-gate MOSFET could be reduced to 3.0 {mu}m, which resulted in an increase in the cell density and in current driving capability. By reducing masks to four layers, a cost-effective process was available. The self-aligned technique also permits a narrow width of the trench gate on the scale of 300 nm. The fabricated device exhibits a specific on-resistance of 1.4 m{Omega}{center_dot}cm{sup 2} for a breakdown voltage of 114.8 V. Moreover, the long-term gate oxide's integrity was improved by adopting corner rounding and hydrogen annealing technologies.

Self-Aligned Amorphous Silicon Thin-Film Transistors Fabricated on Clear Plastic at 300 $^{\circ}\hbox{C}$

We fabricated back-channel-cut and back-channel-passivated hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) on clear-plastic (CP) foil substrates using a silicon nitride (SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">∞</sub> ) deposition temperature of 300°C. The TFTs were fabricated on CP and are as stable under high gate bias as TFTs made on glass substrates. A self-alignment technique was developed to align the channel passivation, the a-Si:H island, and the source/drain (S/D) terminals to the gate. Self-alignment allowed us to fabricate discrete TFTs across 7 7 × cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of a free-standing sheet of CP foil to reduce the TFT channel length L to 3 m and reduce the S/D overlap with the gate L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SD</sub> to ~1. To test the self-alignment techniques, we fabricated ring oscillators on the CP substrates. These results show that it is possible to fabricate state-of-the-art self-aligned a-Si:H TFTs and TFT circuits on plastic substrates.

Self-aligned Process for SiC Power Devices

AbstractSilicon carbide is a semiconductor with desirable material properties, such as a wide bandgap and high thermal conductivity. It is an excellent material for constructing power switching devices operating in harsh environments where conventional semiconductors cannot adequately perform. One example of such a power device is a bipolar junction transistor (BJT). While the potential of the SiC BJT is recognized, appropriate techniques for producing devices is lacking due to its difficulty.For example, in order to achieve a high voltage 4H-SiC BJT switch with nanosecond switching time, the device must have a low base resistance. The simulation results indicate that for an emitter width of 2.0 μm and a base width of 1.2 μm the distance between the two should be 0.4 μm or less to meet the requirement for base resistance. To produce the above-described geometries and spacing, it is desirable to construct the device in a self-aligned manner. Self-alignment in this context means that the relative spacing of features of the device, such as contacts, is automatically controlled by the processing sequence and process parameters, rather than by the careful alignment prior to exposure of a photo sensitive layer. For this purpose, we developed a novel self-aligned process for SiC BJT devices, that enables the fabrication of the design with high yield, as standard silicon self-aligned technique are not applicable.The newly developed process starts with the deposition of the emitter contact metal, which provides the metal mask for the etching of the emitter ridges. Next, the wafer is planarized with photoresist and etched, so that only the emitter contacts are exposed. Electroless plating is then used to enlarge the contacts, and after removal of the resist, the plating provides an overhang, suitable for lift-off of the base contact metal. After the base contact metal deposition, the structure is planarized and etched, this time with a silicon dioxide layer, again exposing the plated emitter contacts and the lift-off step is the wet etching of the plated metal. The emitters are then all connected with a blanket wiring level, which also forms the base contact pad. This process is simpler and more robust than the process we developed to date. The main difference is the inclusion of a sacrificial lift-off overhang, created by electroless plating. It enables a well controlled overhang independent of steepness of the SiC ridge profile and the height of the emitter mesa. We successfully fabricated the overhang structure on 4H-SiC substrates.In conclusion, we report the demonstration of a new self-aligned process, which provides a self-aligned emitter contact, a self-aligned base contact and eliminates the need for via holes smaller than the emitter stripe widths. We consider this new process a major improvement over existing processes to fabricate SiC BJT devices.

Autoconfocal transmission microscopy based on two-photon-induced photocurrent of Si photodiodes

We describe a simple, self-aligned confocal transmission microscopy technique based on two-photon-induced photocurrents of silicon photodiodes. Silicon detectors produce photocurrents in quadratic dependence on incident intensity under the pulsed illumination of light with wavelengths longer than 1.2 microm. We exploit this nonlinear process to reject out-of-focus background and perform depth-sectioning microscopic imaging. We demonstrate a comparable background rejection capability of the technique to linear confocal detection and present three-dimensional imaging in biological specimens.