Self-aligned Technique Research Articles

Self-Aligned Top-Gate Coplanar In-Ga-Zn-O Thin-Film Transistors

Self-aligned techniques are often used in conventional CMOS and Si-based thin-film transistors (TFTs) technologies due to various merits. In this paper, we report self-aligned coplanar top-gate InGaZnO TFTs using PECVD a-SiNinfin:H patterned to have low hydrogen content in the channel region and high hydrogen content in the source/drain region. After annealing to induce hydrogen diffusion from a-SiNinfin:H into the oxide semiconductor, the source-drain regions become more conductive and yet the channel region remains suitable for TFT operation, yielding a working self-aligned TFT structure. Such fabrication involves neither back-side exposure nor ion implantation, and thus may be compatible with the typical and cost-effective TFT manufacturing.

Large-area sub-micron gap interdigitated THz emitters fabricated by interference lithography and angle evaporation

Interference-lithography and a self-aligning angle-evaporation technique are employed to fabricate interdigitated photoconductive terahertz (THz) emitters. The devices have a large active area for high directivity and submicron spaced electrodes for high internal electric fields at low bias voltages. The fabrication process offers the advantage that only one patterning step is needed to generate three isolated metallic structures. This avoids critical alignment and reduces the fabrication effort significantly. Voltage dependent THz emission is observed from 4 V upwards.

Elastic Averaging for Assembly of Three-Dimensional Constructs From Elastomeric Micromolded Layers

Precision engineering has been used in the macroworld and in the microscale only with rigid materials. Soft flexible materials commonly used for microfluidics and other bio-MEMS applications have not been aligned with elastic averaging. We report the use of complementary raised and recessed circular features to align polymer layers and demonstrate alignment accuracy and repeatability. The alignment is accomplished in a Petri dish with a thin layer of liquid between the two surfaces of micromolded elastomeric polymer sheets. The layers are aligned with simple hand-eye manipulation. We test circular geometries of varying diameters, obtaining accuracy and repeatability values in the range of 1-3 mum across thin polymer sheets molded from silicon masters. This is a significant improvement over existing manual, moving stage, and self-alignment techniques and a novel proof of concept that paves the way for complex 3-D polymer constructs.

Silicon optocouplers for biosensing

Here we review on the fabrication and the bioanalytical applications of a monolithic silicon optocoupler that integrates an array of silicon avalanche diodes as light sources, detectors and silicon nitride optical fibres, all intercoupled through a self-alignment technique. The optocoupler is combined with a microfluidic module that allows for simultaneous real-time sensing of multiple analytes. Detection is performed through reaction of the immobilised biomolecules with labelled counterpart molecules. The binding of these molecules within the evanescent field at the surface of the optical fibre causes absorption of the waveguided modes and reduction of the detector photocurrent. The biotin-streptavidin model assay was used for the evaluation of the analytical potentials of the device developed. A detection limit of 3.8 pM in terms of gold nanoparticle labelled streptavidin was achieved which was further improved to 20 fM by silver-plating of the immobilised gold nanoparticles. In addition, results that demonstrate the efficiency of the device for multiple protein and DNA detection are provided. The ability of the developed integrated silicon optocoupler for label-free analyte determinations is also discussed.

Low-Cost, Precision, Self-Alignment Technique for Coupling Laser and Photodiode Arrays to Polymer Waveguide Arrays on Multilayer PCBs

The first, to our knowledge, passive, precision, self-alignment technique for direct coupling of vertical cavity surface emitting laser (VCSEL) and photodiode (PD) arrays to an array of polymer buried channel waveguides on a rigid printed circuit board (PCB) is reported. It gives insertion losses as good as the best achieved previously, to within experimental measurement accuracy, but without the need for costly active alignment nor waveguide facet polishing and so is a major step towards a commercially realizable low cost connector. Such an optical connector with four duplex channels each operating at 10 Gb/s (80 Gb/s aggregate) was designed, constructed, and its alignment precision assessed. The alignment technique is applicable to polymer waveguide interconnections on both rigid and flexible multilayer printed circuit boards (PCBs). The dependence of optical coupling loss on misalignments in , and of the VCSEL and PD arrays allows the precision of alignment to be assessed and its reproducibility on multiple mating cycles of the connector is reported. The first recorded measurements of crosstalk between waveguides when the connector is misaligned are reported. Lateral misalignments of the connector to within its tolerance are shown to have no effect on the signal to crosstalk ratio (SCR), to within experimental measurement accuracy. The insertion loss repeatability is similar to that of single mode fiber mechanically transferable (MT) connectors.

Novel Cost-Effective Photoreceiver Structure with Monolithically-Integrated Polymeric Waveguide Mirrors and Solder Bumps for Future 100-Gbit/s Class Receiver Modules

We propose a new cost-effective structure for a future 100 Gbit/s-class optoelectronic integrated circuit (OEIC) with optical interconnection and a receiver module. This module is a flat compact package and achieves good optical and high-speed electrical performance. A polymeric optical waveguide and a curved micro-mirror are monolithically integrated on the OEIC as the optical interconnection. Furthermore, this OEIC chip is assembled using solder bumps and passively self-aligned technique. We confirmed the feasibility of applying this novel structure to future cost-effective 100-Gbit/s class receiver modules.

Fabrication and Packaging of 40-Gb/s AlGaInAs Multiple-Quantum-Well Electroabsorption Modulated Lasers Based on Identical Epitaxial Layer Scheme

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> High-speed AlGaInAs multiple-quantum-well (MQW) electroabsorption modulated lasers (EMLs) based on an identical epitaxial layer (IEL) integration scheme are developed for 40-Gb/s optical fiber communication systems. A self-aligned planarization technique has been adopted to reduce the capacitance of the electroabsorption modulator (EAM). The IEL structure EML chips exhibit a small signal modulation bandwidth around 40 GHz. The influence of residual reflection at the modulator facet on the small signal modulation response is investigated. Submount containing a grounded coplanar waveguide (GCPW) transmission line is used for packaging the EML chips into transmitter modules. The optimization of the GCPW structure to suppress resonances in frequency response due to parallel-plate modes is presented. Clear eye opening under 40-Gb/s nonreturn-to-zero (NRZ) modulation has been demonstrated for the packaged EML module. </para>

Fabrication of 22nm half-pitch silicon lines by single-exposure self-aligned spatial-frequency doubling

The relentless progression of semiconductor technology to smaller feature sizes will likely soon outstrip the theoretical linear system limits of today’s optical lithography tools (a half-pitch of λ∕4n or 34nm with a 193nm wavelength source and water immersion). We demonstrate a self-aligned process involving only a single lithographic exposure followed by spatial-frequency doubling that results a half-scaling of the original pattern and have achieved a 22nm half-pitch pattern with 193nm water immersion. A lithographic pitch of 89nm was realized with a 193nm ArF-excimer laser source and de-ionized-water immersion interferometric lithography. A self-aligned spatial-frequency doubling technique, taking advantage of the well-known anisotropic etching of silicon by KOH, was used to affect the frequency doubling. A protective layer (metal) was deposited parallel to the (110) direction of a (100) silicon wafer and the sample was immersed in an appropriate KOH solution, resulting in a series of 44.5nm opening width V-grooves terminated in 57° (111) faces etched into the silicon through the mask openings. The metal mask was removed to expose the previously protected high-etch rate (100) surface of the sample for a second wet KOH etch. This results in a pattern at twice the original spatial frequency. A frequency-doubled pitch of 44.5nm was achieved. An alternate, manufacturing friendly, processing scheme related to standard gate sidewall passivation is proposed.

An ultrathin (∼100μm thick) flexible light plate fabricated using self-alignment and lift-off techniques

An ultrathin (∼100μm thick) flexible light plate was designed and fabricated on a parylene template using a combination of self-alignment and lift-off techniques. The solid-state InGaN light-emitting diodes (LEDs) (λp=465nm) was used as the light source to overcome the problem of conventional organic light-emitting devices which require perfect encapsulation against the permeation of water and oxygen. After the sidewalls of LEDs were passivated by the photodefinable polymer, the LED chip array can be further sandwiched by the indium-tin oxide (ITO) and Al electrodes to form a thin-film package with all the processing temperatures below 250°C. The ITO-coated transparent parylene template can be peeled off from the glass carrier after forming the ultrathin LED light plate. The flexible light plates present no damage even after they were flexed 1000 times around a 3-cm-diameter cylinder. The present self-alignment or mask-less process is a very promising approach to flexible backlight applications.

New retroreflector technology for light-collecting systems

A novel retroreflector design using a pseudo-phase-conjugation mirror, viz., a corner cube mirror array (CMA), is proposed for light-collecting systems to increase the apparent brightness of the light source and thus increase the light collection efficiency. Measurement data for a dual paraboloid reflector system using a CMA retroreflector are presented. Design issues for the CMA are discussed. The advantages of the CMA retroreflector are: (1) it is a self-aligning technique, so it works regardless of its shape and position; (2) it is self-compensated for image distortion. Therefore a highly efficient low-cost light collection system with bigger manufacture tolerances is possible.

Ink-jet printed ZnO nanowire field effect transistors

Semiconducting nanowires provide routes for realizing high-performance electronic devices, but for many applications of such devices low-cost manufacturing techniques are needed. The authors demonstrate here top-gated zinc oxide nanowire field effect transistors (NW-FETs) fabricated by ink-jet printing. High resolution submicrometer gold gaps between source and drain electrodes were defined by a self-aligned ink-jet printing technique, and the nanowires were deposited from solution onto these electrode arrays and gated from the top using a spin-coated poly(methyl methacrylate) gate dielectric. The typical NW-FETs exhibited a mobility of 2–4cm2∕Vs, a current on/off ratio of 104, and a transconductance of 20.5nS. The process provides a pathway for fabrication of NW-FETs by low-cost, large-area solution processing and direct printing techniques.

Self-aligned inkjet printing of highly conducting gold electrodes with submicron resolution

Self-aligned printing is a recently developed bottom-up printing technique which utilizes the unique droplet motion on heterogeneous surfaces to define sub-100-nm critical features and surpasses the resolution which can commonly be achieved by direct printing by two orders of magnitude. Here we extend this method, which was originally implemented with conductive polymer inks, to fabrication of functional conductive nanostructures with gold nanoparticle ink. We also designed a configuration where the ink was printed between two lithographically defined patterns to facilitate the study of the channel formation. Channel lengths from 4μm down to 60nm were achieved by controlling the surface tension and drying time of the ink. A fluid dynamical model is presented to explain the mechanism by which the channel forms in the self-aligned printing technique. Field-effect transistors fabricated using gold self-aligned printed source-drain electrodes exhibit significantly improved output currents than those using conducting polymers. Unambiguous evidence for the submicrometer channel dimension is obtained by imaging the potential drop along the channel using scanning Kelvin probe microscopy.

High Performance 1.55 μm InGaAsP Buried-Heterostructure Laser Diodes Fabricated by Single-Step MOCVD Regrowth and Self-Aligned Technique

In this article, we demonstrate a simple and low-cost method to fabricate the strained multiquantum-well buried-heterostructure (BH) laser diodes (LDs) by using the single-step metallorganic-chemical-vapor-deposition (MOCVD) regrowth and self-aligned technique. The active region is buried by the intrinsic layer which is used as the current-blocking layer as well as the electrical and optical confinement layer. The BH LDs have a calculated internal quantum efficiency of 81% and an internal loss of . The fabricated as-cleaved BH LDs exhibit a threshold current of , a maximum light output power of at , a maximum operating temperature of , and a characteristic temperature of in . The BH LDs with an as-cleaved front facet and a high reflectivity coating applied to the rear facet can increase the maximum operation temperature up to and have a light output power exceeding at and . The frequency at a bias current of is 8.0, 6.5, and at 30, 60, and , respectively. Besides, the modulation bandwidth can be extended as far as at and . These results confirm that BH LDs have the potential capacity for high-speed fiber optic applications.

Self-aligned TiSi2/Si Hetero-nanocrystal Nonvolatile Memory

AbstractThis work describes a novel nonvolatile memory device with self-aligned TiSi2/Si hetero-nanocrystal charge storage nodes. The TiSi2/Si hetero-nanocrystals can be readily fabricated using industrial standard self-aligned silicidation technique based on Si nanocrystals deposited on ultra-thin tunnel oxide with LPCVD. As compared with a Si nanocrystal memory device, a TiSi2/Si hetero-nanocrystal memory device exhibits faster programming and erasing, and longer retention time.

Multiple Self-Aligned Iron Nanowires by a Dual Selective Chemical Vapor Deposition Process

have also been reported. In this paper, we demonstrate a self-aligning technique that allows the fabrication of organized parallel iron nanowires on a planar edge silicon and silicon dioxide surface. The desired number of parallel wires is formed by repeating a series of polysilicon deposition and oxidation steps. The planarized surface for nanowire formation was defined by CMP and the iron wires were produced using a novel double selective CVD process. In this work, tungsten hexafluoride WF6 and iron pentacarbonyl FeCO5 were the respective tungsten and iron precursors. The dimensions and spacing of the iron wires were determined by the thickness of the thermal oxide and deposited polysilicon layer respectively, and not by any lithographic tool. Very accurate alignment was achieved with this method. The multiple iron nanowires proposed in this paper have possible applications in magnetic field measurement and calibration devices in pressure sensing where the resistivity of long thin iron resistors changes under stress. Possibly the most interesting application for this technology is in the formation of tunable diffraction gratings. Under the influence of an electromagnetic field, the properties of the iron will change, which may allow a switching mode in the grating. Figure 1 shows substrate preparation and the deposition of multiple parallel iron nanowires. 4 m deep trenches were etched into the silicon substrates in an inductively coupled plasma ICP system with SF6 and C4F8 plasmas Fig. 1a. The trenches were then refilled

Ti Si 2 ∕ Si heteronanocrystal metal-oxide-semiconductor-field-effect-transistor memory

Ti Si 2 ∕ Si heteronanocrystals with a density of 5×1011cm−2 were formed on a thermally oxidized p-type Si substrate by using self-aligned silicide technique. Metal-oxide-semiconductor-field-effect-transistor (MOSFET) memory devices were fabricated using these heteronanocrystals as floating gates. As compared to Si nanocrystal MOSFET memory, TiSi2∕Si heteronanocrystal memories exhibit higher charge storage capacity, longer retention, better writing efficiency, less writing saturation, and faster erasing speed.

A novel self-aligned process between a nano-aperture and a solid immersion lens for a near-field optical system

For near-field optical systems, an aperture in nano-size and a solid immersion lens (SIL) are two popular methods to overcome the diffraction limit and reduce the optical spot size. In previous research, combining a nano-aperture and SIL has been proposed to provide high throughput and ultra-high resolution. However, alignment between the nano-aperture and SIL is very critical in the fabrication process, and no effective alignment technique has been investigated yet. In this research, a novel self-alignment technique is proposed for the combination of the nano-aperture and SIL, where the nano-aperture is fabricated with the focused ion beam (FIB) system and the SIL is formed by the thermal reflowing process. The self-alignment technique is based on the backside exposure and the surface tension self-modulation technique during the thermal reflowing process. The maximum deviation of the fabricated SIL is less than 3% in comparison with the designed values. A SIL of 15 µm diameter has been measured with 65.2% transmission efficiency. The polymer SIL combined with the circular aperture of 329 nm diameter has 1.68 times enhancement on throughput compared with the circular aperture of 329 nm alone. This result shows that the SIL can effectively enhance the throughput of the nano-aperture, and the feasibility of the proposed self-alignment method is also verified.

Chemically responsive molecular transistors fabricated by self-aligned lithography and chemical self-assembly

The authors present the fabrication and characterization of molecular transistors comprising at most a small number of molecules, which display a distinct chemical function. The fabrication involves a self-aligned technique capable of patterning metal electrodes with interelectrode separations of ∼2nm with very high yield. The electrodes are bridged by molecules with a metal-ion core which can be inserted by in situ designed chemical reaction. The presence or absence of the ion modulates the electrical conductance of the device.

Fabrication of high-speed InP/InGaAs/InP DHBT with a new self-aligned metallization technique for reduced base resistance

A new self-aligned emitter–base metallization (SAEBM) technique with wet etch is developed for high-speed heterojunction bipolar transistors (HBTs) by reducing extrinsic base resistance. After mesa etch of the base layer using a photo-resist mask, the base and emitter metals are evaporated simultaneously to reduce the emitter–base gap (SEB) and base gap resistance (RGAP). The InP/InGaAs/InP double heterojunction bipolar transistor (DHBT) fabricated using the technique has a reduced RGAP, from 16.48Ω to 4.62Ω comparing with the DHBT fabricated by conventional self-aligned base metallization (SABM) process. Furthermore, we adopt a novel collector undercut technique using selective etching nature of InP and InGaAs to reduce collector–base capacitance (CCB). Due to the reduced RGAP, the maximum oscillation frequency (fmax) for a 0.5μm-emitter HBT is improved from 205GHz to 295GHz, while the cutoff frequency (fT) is maintained at around 300GHz.

Fabrication and characterization of 3-Dimensional MOS transistor tip integrated micro cantilever

We fabricate and characterize a three-dimensional (3-D) MOS (metal–oxide–semiconductor) transistor tip integrated micro cantilever to measure the surface properties. The 3-D MOS transistor tip is fabricated on the front side end of the cantilever, and the cantilever itself works as a tip. These features make the device possible to investigate hard-detecting parts such as the deep trenches and the sidewalls of the structure. The MOS transistor tip has other advantages such as the high operation speed, the high sensitivity, and the reduction of the required equipments like the lock-in-amplifier. The MOS transistor tip is fabricated three-dimensionally, utilizing the lateral diffusion and the anisotropic wet etching with TMAH solution, since the etch rate of {211} plane is much higher than those of {100} or {111} planes. The gate area is formed by self-aligned technique, using crystallographic dependant wet etching. The well-known convex corner compensation pattern is used for the gate length control during the tip fabrication process. The characteristics of the fabricated device are measured with respect to the various electric signals and the results show the well-established detection properties.