Self-aligned Structure Research Articles

Fully logical NOT operation of self-aligned liquid crystal optical control devices with two-slit Young’s interference experiment

ABSTRACT Liquid crystal devices have been in practical use for more than half a century and are now widely used as low-voltage, low-power-consumption displays and optical elements. We have confirmed the partial NOT logic operation of some optical interference peaks in two-slit Young’s interference experiments using a liquid crystal device with a self-aligned structure. In this report, we report that we were able to obtain a fully NOT logic operation of the entire optical interference pattern by investigating the liquid crystal alignment of antiparallel direction.

Self-Aligned Top-Gate Structure in High-Performance 2D p-FETs via van der Waals Integration and Contact Spacer Doping.

The potential of 2D materials in future CMOS technology is hindered by the lack of high-performance p-type field effect transistors (p-FETs). While utilization of the top-gate (TG) structure with a p-doped spacer area offers a solution to this challenge, the design and device processing to form gate stacks pose serious challenges in realization of ideal p-FETs and PMOS inverters. This study presents a novel approach to address these challenges by fabricating lateral p+-p-p+ junction WSe2 FETs with self-aligned TG stacks in which desired junction is formed by van der Waals (vdW) integration and selective oxygen plasma-doping into spacer regions. The exceptional electrostatic controllability with a high on/off current ratio and small subthreshold swing (SS) of plasma doped p-FETs is achieved with the self-aligned metal/hBN gate stacks. To demonstrate the effectiveness of our approach, we construct a PMOS inverter using this device architecture, which exhibits a remarkably low power consumption of approximately 4.5 nW.

Quarter-Micron Alignment of Chiplets via Positive Self-Aligned Structures

Quarter-Micron Alignment of Chiplets via Positive Self-Aligned Structures

Scaling carbon nanotube field effect transistors to 30 nm channel length on pretreated PET

With the extensive application of flexible circuits to artificial intelligence (AI) and the internet of things (IoT), high requirements have been promoted for the integration and miniaturization of flexible circuits. However, the vast majority of transistors on flexible substrates reported so far have micrometer-level channel length (Lch), seriously affecting the integration abilities of flexible circuits. In this work, we explore the scaling behaviors of flexible carbon nanotube field effect transistors (CNT FETs) by fabricating p-type flexible CNT FETs with Lch varying from 2 μm to 70 nm on polyethylene terephthalate (PET) substrates. The improved width-normalized on-state current (Ion/Wch), transconductance (gm) and near-constant gate efficiency indicate that CNTs have great potential in constructing ultra-small flexible FETs. Additionally, we fabricate a CNT FET with a 30-nm channel length on a cleaned PET substrate using a self-aligned top-gate structure; this CNT FET can achieve a high on-state performance of 103 μA/μm when Vds = −0.8 V. The pitch size of the device is 230 nm, which is the smallest size of flexible transistors so far. Even with deep submicron and nanometer channel lengths, the yields of flexible CNT FETs can reach 60% (33/56); which is benefiting from the pretreated substrate, demonstrating the potential for large-scale production.

Fabrication and Characterization of Self-Aligned WSe2 p-Type Field-Effect Transistor

Semiconducting transition metal dichalcogenides (TMDCs) have been growing interests as channel materials in field effect transistors (FET) for next generation low power digital electronics. [1]. Since a complementary metal oxide-semiconductor (CMOS) inverter constructed from pairs of n-type and p-type FETs is a fundamental building blocks in modern digital electronics [2], implementation of both n-type and p-type FETs with semiconducting TMDCs is of particular importance [3]. Among various semiconducting TMDCs, tungsten diselenide (WSe2) is a promising candidate for constructing a CMOS inverter because of its high mobility, symmetric electron and hole effective mass and ambipolar transport [4]. These prominent features of WSe2 is suitable for an application to CMOS inverter.One of the significant challenges is to develop a top gate and top contact FET structure with WSe2 for CMOS device integration on the same wafer. In addition, it is desirable to minimize the access region between channel and S/D contact because this access region served as a series resistance to channel resistance, resulting in the lower drain current in FET. This study reports a self-aligned process to fabricate top gate and top contact WSe2 p-type FET. In this self-aligned structure, the gate electrode and source/drain contact edges are automatically positioned and hence there are no overlap or access region between the gate and source/drain. The feature of this proposed method is that the gate stacks was utilized as a mask for self-aligned formation of WOx, which is source/drain contact for efficient hole injection [5]. The focus on this study is the impact of self-aligned structure of p-type WSe2 FET on the electrical characteristics. The effectiveness of proposed process was experimentally demonstrated by the fabrication and characterization of device.Figures 1 shows the self-aligned fabrication process of p-type WSe2 FET. 20 nm-thick SiO2 was formed by dry oxidation of p+-Si substrate. The mechanically exfoliated multi-layer WSe2 was transferred by PDMS stamp. Next, 15 nm-thick Al2O3 was prepared by ALD at 200 oC with H2O. Then, Nickel (Ni) metal was deposited by RF sputtering on Al2O3. Ni metal was patterned for gate electrode with conventional lithography process. After that, A2O3 layer was removed by wet etching. Subsequently, substrate was exposed to oxygen radicals to form WOx used as source/drain contact at surface of WSe2. Second layer of Al2O3 was deposited as an encapsulating passivation layer. After the contact hole opening, the electrical contact pad was fabricated. Finally, forming gas (N2 : H2 = 97 % : 3 %) annealing was performed at 200 oC for 30 min. The top gate length was 5 μm. The gate width was estimated to be 40 μm by optical microscope. The electrical characteristics were measured with a manual probe station in an atmospheric pressure without inert gas purge at room temperature using a precision semiconductor parameter analyzer (Agilent 4156 C).Figures 2 shows the Id–Vg characteristics of fabricated FETs for (a) back gate operation and (b) top gate operation. Representative Id–Vg characteristics of p-type FETs were observed irrespective of back gate and top gate operation. The on/off ratio of about 106 ~ 107 order were obtained for both back gate and top gate operation. Furthermore, the threshold voltage and sub-threshold slope were modulated by varying the substrate bias during gate sweep.This study opens up interesting directions for the research and development of TMDC-based devices.AcknowledgmentsThis study was supported by a JSPS Grant-in-Aid for Scientific Research (C) (Grant No. 20K04616), a research grant for Tokyo Tech Challenging Research Award, the Samco Foundation and a research grant for Suematsu Award.

Investigation on Recrystallization Channel for Vertical C-Shaped-Channel Nanosheet FETs by Laser Annealing.

Transistor scaling has become increasingly difficult in the dynamic random access memory (DRAM). However, vertical devices will be good candidates for 4F2 DRAM cell transistors (F = pitch/2). Most vertical devices are facing some technical challenges. For example, the gate length cannot be precisely controlled, and the gate and the source/drain of the device cannot be aligned. Recrystallization-based vertical C-shaped-channel nanosheet field-effect transistors (RC-VCNFETs) were fabricated. The critical process modules of the RC-VCNFETs were developed as well. The RC-VCNFET with a self-aligned gate structure has excellent device performance, and its subthreshold swing (SS) is 62.91 mV/dec. Drain-induced barrier lowering (DIBL) is 6.16 mV/V.

Studies of Electrical Parameters and Thermal Stability of HiPIMS Hafnium Oxynitride (HfOxNy) Thin Films

This work demonstrated the optimization of HiPIMS reactive magnetron sputtering of hafnium oxynitride (HfOxNy) thin films. During the optimization procedure, employing Taguchi orthogonal tables, the parameters of examined dielectric films were explored, utilizing optical methods (spectroscopic ellipsometry and refractometry), electrical characterization (C-V, I-V measurements of MOS structures), and structural investigation (AFM, XRD, XPS). The thermal stability of fabricated HfOxNy layers, up to 800 °C, was also investigated. The presented results demonstrated the correctness of the optimization methodology. The results also demonstrated the significant stability of hafnia-based layers at up to 800 °C. No electrical parameters or surface morphology deteriorations were demonstrated. The structural analysis revealed comparable electrical properties and significantly greater immunity to high-temperature treatment in HfOxNy layers formed using HiPIMS, as compared to those formed using the standard pulsed magnetron sputtering technique. The results presented in this study confirmed that the investigated hafnium oxynitride films, fabricated through the HiPIMS process, could potentially be used as a thermally-stable gate dielectric in self-aligned MOS structures and devices.

Junctionless nanosheet gate‐all‐around transistors fabricated on void embedded silicon on insulator substrate

A novel junctionless gate-all-around (GAA) transistor with ultrathin nanosheet GAA channel and self-aligned raised source/drain (RSD) is successfully designed and fabricated on void embedded silicon on insulator (VESOI) substrate through a much simpler fabrication process. Devices with as thin as 13-nm nanosheet GAA channel thickness exhibit excellent electrical characteristics: on/off current ratio of 106 and on-state drive current of 58 µA/µm. Although the parasitic planar channel component still exists, the device performance is decisively dominated by the GAA channel, and further boosted by the junction-free bulk conduction mechanism and the self-aligned RSD structure.

High-power diode lasers with in-situ-structured lateral current blocking for improved threshold, efficiency and brightness

We present high-power GaAs-based broad-area diode lasers with a novel variant of the enhanced self-aligned lateral structure ‘eSAS’, having a strongly reduced lasing threshold and improved peak conversion efficiency and beam quality in comparison to their standard gain-guided counterparts. To realize this new variant (eSAS-V2), a two-step epitaxial growth process involving in situ etching is used to integrate current-blocking layers, optimized for tunnel current suppression, within the p-Al0.8GaAs cladding layer of an extreme-triple-asymmetric epitaxial structure with a thin p-side waveguide. The blocking layers are thus in close proximity to the active zone, resulting in strong suppression of current spreading and lateral carrier accumulation. eSAS-V2 devices with 4 mm resonator length and varying stripe widths are characterized and compared to previous eSAS variant (eSAS-V1) as well as gain-guided reference devices, all having the same dimensions and epitaxial structure. Measurement results show that the new eSAS-V2 variant eliminates an estimated 89% of lateral current spreading, resulting in a strong threshold current reduction of 29% at 90 μm stripe width, while slope and series resistance are broadly unchanged. The novel eSAS-V2 devices also maintain high conversion efficiency up to high continuous-wave optical power, with an exemplary 90 μm device having 51.5% at 20 W. Near-field width is significantly narrowed in both eSAS variants, but eSAS-V2 exhibits a wider far-field angle, consistent with the presence of index guiding. Nonetheless, eSAS-V2 achieves higher beam quality and lateral brightness than gain-guided reference devices, but the index guiding in this realization prevents it from surpassing eSAS-V1. Overall, the different performance benefits of the eSAS approach are clearly demonstrated.

Self-Aligned Organic Metal–Semiconductor Field-Effect Transistor

We propose the design and fabrication of a coplanar electrode structure for an organic metal–semiconductor field-effect transistor (OMESFET), with the gate electrode self-aligned between the source and drain electrodes. We first used nanoimprint lithography (NIL) to define a channel area of the device on a patterned metal, and then used chemical wet etching to create the source and drain electrodes by removing the metal in the channel area. After the wet etching, the gate electrode was deposited in the channel area. The organic semiconductor was then deposited to cover the patterned electrodes. The rectifying response and the device characteristics prove that the self-aligned device is a functional OMESFET. In this experiment, we also demonstrated that the self-aligned OMESFET has lower driving voltages and smaller subthreshold swing (SS) than that of a conventional organic metal–insulator–semiconductor field-effect transistor (OMISFET). Compared with the most common OMESFET structure, this self-aligned coplanar structure effectively eliminates the overlapping area between the gate and source/drain electrodes commonly seen in currently reported OMESFETs, which means that this self-aligned device structure reduces the parasitic capacitance, theoretically allowing the transistor to have a higher cutoff frequency. These features render our proposed OMESFET devices more favorable for low-power and high-frequency organic circuit applications.

Electrical Performance Enhancement of Fully Solution-processed Amorphous In-Zn-O Thin-Film Transistor via Argon Plasma Treatment

Amorphous oxide semiconductors are intensively studied nowadays due to its excellent material characteristics, such as high mobility, high optical transparency, large area uniformity, and low processing temperature which enable flexible device application [1]. Solution approach is a promising method over conventional vacuum process, because of its simplicity and versatility with high material utilization which can minimize fabrication cost [2]. To optimize for application in flexible substrates, reduction of process temperatures to <400oC is an important requirement. Plasma treatment can be used to modify thin-film properties and device characteristics by modulating carrier concentration and density of oxygen vacancies [3]. Argon plasma treatment can improve reliability, as carbon concentration on the surface can be reduced, and oxidation enhancement on the surface can be achieved. This research aims to study the effect of plasma treatment on the stability of fully solution processed amorphous Indium Zinc Oxide (a-IZO) thin-film transistor (TFT).Our fully solution processed a-IZO TFTs were fabricated with a self-aligned top gate structure at a maximum fabrication temperature of 300oC. Initially, IZO precursor was spin-coated on Si/SiO2 substrate. Then, fluorinated-polysilsesquioxane (F-PSQ) was deposited with a thickness of ~200 nm which act as a gate-insulator, followed by an IZO layer to be transformed as conducting electrode after treatment. Self-aligned patterning, gate etching, and gate insulator etching were then performed. Lastly, Argon plasma treatment is performed via inductively coupled plasma (ICP), using reactive ion etching SAMCO 10-ip equipment for 5 seconds at room temperature with an ICP power, bias power, and working pressure of 300 W, 100 W, and 5 Pa, respectively. The Argon flow rate was also varied at 100, 75, and 50 sccm. The IZO TFT without plasma treatment was denoted as-fabricated sample. After plasma treatment, exposed IZO layers transform as source/drain and gate. TFT structure before and after plasma treatment can be seen in Fig. 1.Film surface morphology was studied using atomic force microscopy. As Argon concentration increased, the exposed IZO surface became rougher. We also checked the transfer characteristics, performed cyclic measurement, and bias stress tests. Transfer characteristics of TFTs with 90µm width and 10µm length were examined at several drain voltages (Vd = 0.1 V, 5.0 V, and 9.9 V) by a semiconductor parameter analyzer. Transfer curves for as-fabricated and after Ar-75 plasma treatment are shown in Fig 1. As-fabricated sample shows poor switching characteristics because of inactivated source/drain and gate electrodes. After plasma treatment, TFTs show superb characteristics which possibly happened because of changes in the metal-oxide bond formation which increased the conductivity in exposed area. The mobility significantly increased to 31.12 cm2/Vs, with a Vth= -0.3 V and subthreshold swing of 0.28 V/dec for Ar-75 sccm. TFT yield was evaluated by measuring 8 TFTs for each sample. Average mobility for Ar-50, Ar-75, and Ar-100 is 20.30 cm2/Vs, 22.93 cm2/Vs, and 19.88 cm2/Vs, respectively. The mobility increase corresponded to the thin-film quality improvement caused by change in VO and surface roughness [4]. However, excessive Argon gas flow also tend to make samples more conductive.To investigate device stability, positive bias stress (PBS, stress V g= 10 V) and negative bias stress (NBS, stress V g= -10 V) was performed for 2,000s. Lower on-current for all samples were observed as bias stress duration increased. A threshold voltage shift (∆Vth) for Ar-50, Ar-75, and Ar-100 of 0.2 V, -0.3 V, and 0.6 V, respectively after PBS, and 1.4 V, 2.9 V, and 0.7 V, respectively after NBS was observed. We expect that improvement via plasma treatment is due to two main factors. First, ion bombardment caused surface improvement and activated the electrode. Second, the chemical reaction induced by plasma treatment changed the metal-oxide bonds formation [5-6]. Thus, fully solution-processed a-IZO TFT with high mobility up to 31.12 cm2/Vs was achieved by Ar-75 plasma treatment, which also led to better stability under bias stress. These results show that performance enhancement of fully-solution processed a-IZO TFT by plasma treatment has a large potential for future low-temperature flexible device applications.Acknowledgment:This research was supported by JSPS Kakenhi Grant no. 22K14291. The authors thank Nissan Chemical Corporation for providing the IZO precursor solution.

Cu Deposition on AAO Substrate for Interposer Applications

In recent days, the demand for high-performance devices has increased in the semiconductor industry. These devices require integrated circuits to test out their performance. For this purpose, interposer with both vertical and horizontal copper circuits which offers advanced connections is used. Interposer consists of a substrate material and metal circuits. Common substrate materials for the interposer are silicon and glass. Whereas anodized aluminum oxide (AAO) has less current leakage than silicon substrate, which results in no need for the insulation, and has a vertically self-aligned nanopore structure though wet etching process, which enables high density holes with less cost. AAO was proposed as a substrate material for interposer.AAO substrate was fabricated using 0.3M oxalic acid solution, followed by fabricating through-hole of AAO. For the interconnection, copper layer was deposited on the surface and hole of AAO substrate by electroless and electrochemical techniques sequentially. Sol-gel catalyst was adopted followed by heat treatment, instead of Sn/Pd catalyzation, to increase the adhesion property and breakdown voltage. Fabricated AAO is a circle shape with 4.8 cm diameter and average pore size is about 98 nm. Cu electroless deposition was performed on AAO with and without through-holes. Thin Cu layer was deposited without voids. The adhesion was measured by SCRATCH TESTER PRO, J&L Tech, Korea, showing first crack around 1.5 N to 2 N. Pulse electrodeposition with surfactant was used to fill the trough-hole of AAO substrate for through-AAO interconnects. The more details will be presented. Figure 1

(Invited) High Performance Fully Solution Processed Transistors Towards Flexible Sustainable Electronics

High performance fully solution-processed amorphous InZnO (a-IZO) thin-film transistors (TFT) were fabricated using low temperature processes such as ultraviolet (UV) treatment, excimer laser annealing (ELA), continuous wave (CW) laser irradiation, and Ar plasma treatment. By employing a self-aligned top-gate structure, these processes can selectively functionalize the IZO semiconductor into conductive electrodes. Thus, a single IZO layer can simultaneously act as both the channel and source/drain electrode. Depending on the low temperature process employed, mobilities of up to 40 cm2 V-1 s-1 can be achieved with low turn on-voltage of -0.4 V and subthreshold swing of 0.2 V dec-1 which is comparable to TFTs fabricated by vacuum process. The low temperature approach also enabled the fabrication of fully solution processed a-IZO TFTs on flexible substrates. Comprehensive analysis of several characterization results suggests that both fluorine and oxygen vacancies play a major role in the high performance fully solution processed a-IZO TFTs.

High-Performance GaN Vertical Schottky Barrier Diode With Self-Alignment Trench Structure

In this work, high-performance GaN vertical Schottky barrier diodes (SBDs) are successfully fabricated on the GaN-on-GaN substrate by using the self-alignment trench structure and argon (Ar) ion implantation. The fabricated diodes achieve a high current ON/ OFF ratio of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> and high breakdown voltage (BV) of 656 V due to the reduced surface electric field effect. Besides, the temperature-dependent reverse leakage characteristics show that two Poole–Frenkel emission (PFE) processes dominate the carrier transport. This work shows great potential of the self-alignment trench structure in fabricating GaN vertical SBDs to improve the BV with simply fabrication process.

Electrically Self-Aligned, Reconfigurable Test Structure Using WSe2/SnSe2 Heterojunction for TFET and MOSFET

Achieving a self-aligned structure has been an essential key to the development of silicon-based MOSFET technology over the past several decades. However, it is usually challenging to achieve such self-alignment in layered material-based devices due to the lack of conventional doping processes such as ion implantation. In this work, we demonstrate an electrically defined self-aligned test structure using two partially overlapping top gates and a bottom gate in a WSe <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /SnSe <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> van der Waals (vdW) heterojunction. The test structure allows us to discern the properties of the heterojunction without any confounding series resistance effect arising from the WSe <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /metal contact junction. By controlling the individual gates in the test structure, we reconfigurably achieve both p-type TFET operation with a minimum subthreshold slope < 60 mV/decade and n-type MOSFET operation. The structure will be useful to test self-aligned device operations in layered materials without the confounding effect of gate-dependent large contact resistance.

An advanced radio-frequency quadrupole ion cooler for accelerator mass spectrometry

An advanced radio-frequency quadrupole (RFQ) ion cooler was developed for accelerator mass spectrometry to use element-selective laser photodetachment and ion-molecule reactions for isobar suppression. The system will be installed as a central part of the new Anion Laser Isobar Separator (ALIS) at the 6 MV AMS system of CologneAMS.The new RFQ design intends to solve the technical challenge of the deceleration and trapping of heavy molecular ion beams with high emittance. Therefore, an elliptical injection electrode was developed to slow down the ions far away from the central entrance aperture. A new and easy-to-manufacture guide-field assembly was developed. For this purpose, diagonally-split cylindrical surface electrodes are capacitively coupled to a core rod that is carrying the RF signal. Consequently, only low DC voltages are needed to create a gradually changing potential in the longitudinal direction. The RFQ and the acceleration electrodes are installed in a self-aligned structure.

Control of Hydrogen Concentration in Ingazno Thin Film Using Cryopumping System

Recently, amorphous metal-oxide semiconductors (AOSs) such as indium gallium zinc oxide (IGZO) have attracted great attention with their lower power consumption and higher mobility than amorphous silicon in the display field. However, the threshold voltage (Vth) shift of IGZO thin film transistor (TFT) caused by their poor reliability leads to the drop panel luminance. Therefore, improvement of IGZO TFT reliability is necessary, which is largely influenced by oxygen vacancy and hydrogen. In particular, hydrogen has shown different roles inside the IGZO active layer by hydrogen concentration. At lower concentration, the hydrogen passivation of oxygen deficiency region induces the improvement of initial electrical characteristics and reliability [2]. Meanwhile, Vth shift and degradation reliability are generated at higher concentration owing to the hydrogen related defect states [3]. Therefore, controlling excess hydrogen is necessary for reliability enhancement.In this work, IGZO thin film was fabricated by cryopumping system instead of a turbo molecular pump (TMP) for radio frequency sputtering to reduce hydrogen concentration. Cryopump is an adsorption type that enables excellent evacuation ability of hydrogen and moisture taking up most of the partial pressure in high vacuum. As a result, deposition of IGZO thin film with lower hydrogen impurity is available. The hydrogen concentration in the IGZO thin film using both cryopump and TMP was quantitatively analyzed by elastic recoil detection (ERD) analysis. Then, electrical characteristics of the self-aligned top-gate structure TFTs fabricated by both pumps were measured with bias stress conditions.To sum up, we showed the improved reliability of IGZO TFT by controlling excess hydrogen using cryopumping system. Fig.1. (a) Schematic of RF magnetron sputtering process with cryopump. (b) TOF-SIMS depth profiles of hydrogen concentration in IGZO film using TMP and cryopump Acknowledgment This work was supported by the Korea Evaluation Institute of Industrial Technology(KEIT) grant funded by the Korea government (MOTIE) (No. 2021-11-1283) References Chung, Ui-Jin, et al. "15‐1: Invited Paper: Manufacturing Technology of LTPO TFT." SID Symposium Digest of Technical Papers. Vol. 51. No. 1. 2020.Hanyu, Yuichiro, et al. "Hydrogen passivation of electron trap in amorphous In-Ga-Zn-O thin-film transistors." Applied Physics Letters 103.20 (2013): 202114.Mativenga, Mallory, et al. "Origin of light instability in amorphous IGZO thin-film transistors and its suppression." Scientific reports 11.1 (2021): 1-12 Figure 1

A self-aligned lithography method based on Fabry-Perot resonator effect

Fabry-Perot (F-P) resonator is widely applied in the field of optics such as micro-ring resonator and photonic crystal, but there are not yet relevant reports about optical imaging. We propose a self-aligned lithography method based on F-P resonator effect and realize self-aligned effect successfully by controlling film stack parameters. The self-aligned structure is composed of Ag/photoresist/Ag film stack and wafer layer which contains SiO2 layer and SiO2/Si gratings. A rapid simulation model based on Rigorous Coupled Wave Analysis algorithm is established to optimize the best parameters of the self-aligned structure. Then rigorous Finite Difference Time Domain model and Finite Element Method model are used to verify the self-aligned effect and the results show that such process has extremely large mask critical dimension (CD) and overlay variation. The mask CD could be tuned more than 50% of structure period while the wafer CD maintains in the range less than 10%, and the maximum mask overlay offset could be ± 25% of half pitch while the wafer pattern center maintains unchanged. All the results show that the proposed method has lots of process robustness and could increase the application area of imaging lithography technology.

Cation Composition-Dependent Device Performance and Positive Bias Instability of Self-Aligned Oxide Semiconductor Thin-Film Transistors: Including Oxygen and Hydrogen Effect.

Amorphous oxide semiconductor transistors control the illuminance of pixels in an ecosystem of displays from large-screen TVs to wearable devices. To satisfy application-specific requirements, oxide semiconductor transistors of various cation compositions have been explored. However, a comprehensive study has not been carried out where the influence of cation composition, oxygen, and hydrogen on device characteristics and stability is systematically quantified, using commercial-grade process technology. In this study, we fabricate self-aligned top-gate structure thin-film transistors with three oxide semiconductor materials, InGaZnO (In/Ga/Zn = 1:1:1), In-rich InGaZnO, and InZnO, having mobility values of 10, 27, and 40 cm2/V·s, respectively. Combinations of varied amounts of oxygen and hydrogen are incorporated into each transistor by controlling the fabrication process to study the effect of these gaseous elements on the physical nature of the channel material. Electrons can be captured by peroxy linkage (O22-) or undercoordinated In (In* to become In+), which are manifested in the extracted subgap density-of-states profile and first-principles calculations. Energy difference between electron-trapped In+ and O22- σ* is the smallest for IGZO, and In+-O22- annihilation occurs by electron excitation from the subgap In+ state to the O22- σ*. Furthermore, characteristic time constants during positive bias stress and recovery reveal the various microscopic physical phenomena within the transistor structure between different cation compositions.

A Substrate-Agnostic, Submicrometer PSAS-to-PSAS Self-Alignment Technology for Heterogeneous Integration

This paper presents a novel substrate-agnostic self-alignment technology with submicron alignment accuracy targeted for heterogeneous integrated systems. This self-alignment technology, referred to as PSAS-to-PSAS self-alignment, incorporates positive self-alignment structures (PSAS) or reflowed patterned photoresist structures that couple with other PSAS to achieve submicron alignment accuracy without the need for an advanced placement tool. The PSAS-to-PSAS self-alignment technology is non-substrate invasive and hence does not consume any substrate real estate. These PSAS structures can also be fabricated atop any material substrate; hence, this technology is suitable for heterogeneous integrated systems where a variety of different material substrates may be incorporated. This paper discusses this PSAS-to-PSAS self-alignment technology and it provides a design analysis relating the inter-substrate gap between aligning substrates and the dimensions of the PSAS structures. The fabrication of the PSAS on two separate substrates is then performed, followed by a manual assembly process to couple the PSAS on one substrate to the PSAS on the other aligning substrate. Vernier scales are incorporated on these substrates to measure the misalignment between said substrates; submicron alignment is recorded. As these structures may also enable a non-permanent system configuration, alignment repeatability measurements were also performed.