Electrically Self-Aligned, Reconfigurable Test Structure Using WSe2/SnSe2 Heterojunction for TFET and MOSFET

Abstract

Achieving a self-aligned structure has been an essential key to the development of silicon-based MOSFET technology over the past several decades. However, it is usually challenging to achieve such self-alignment in layered material-based devices due to the lack of conventional doping processes such as ion implantation. In this work, we demonstrate an electrically defined self-aligned test structure using two partially overlapping top gates and a bottom gate in a WSe <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /SnSe <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> van der Waals (vdW) heterojunction. The test structure allows us to discern the properties of the heterojunction without any confounding series resistance effect arising from the WSe <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /metal contact junction. By controlling the individual gates in the test structure, we reconfigurably achieve both p-type TFET operation with a minimum subthreshold slope < 60 mV/decade and n-type MOSFET operation. The structure will be useful to test self-aligned device operations in layered materials without the confounding effect of gate-dependent large contact resistance.