Self-aligned Silicide Research Articles

Fluid-kinetics enhanced selective etching process of NiPt film by piranha chemistry in silicide formation for complementary metal oxide semiconductor fabrication

NiPtSi is a prime candidate for the complementary metal-oxide-semiconductors CMOS self-aligned silicidation process beyond the 22nm node. The formation of NiPt silicide in smaller geometries demands more Platinum (Pt) additive to control the silicide quality and a more capable NiPt selective etching process to remove surface residual metals for complementing the formation of silicide. Both higher Pt selective etch rate and lower surface material loss are desired in NiPt selective etching process.High temperature (>150°C) sulfuric acid base piranha chemistry in fresh dispensing on wafer can etch Pt with less damage to the exposed wafer surface. By using (1) a larger mass-to-charge density Pt redox reaction zone in the electrochemistry spectrum of the Pt redox behavior, (2) stronger chemical fluid kinetics and (3) intensified voltammetric cycles, the Pt selective removal rate can be boosted. Two types of wet chemical processors are used to examine the fluid-chemical kinetics effect on the Pt selective etching rate. It is shown that higher chemical flow rates and stronger fluid-kinetics can enhance the Pt transport behavior. The collateral wafer surface material loss rate also increases by higher chemical flow rates, but the amount of total material loss actually reduces due to a greater reduction in the required process time. The fluid-kinetics enhanced selective etching process can cover a wider range of NiPt film conditions (5% Pt, up to 200Å, 10% Pt up to 180Å).

Label-Free and Real-Time Immunodetection of the Avian Influenza A Hemagglutinin Peptide Using a Silicon Field-Effect Transistor Fabricated by a Nickel Self-Aligned Silicide Process

Electrical immunodetection of the avian influenza A (H5N1) hemagglutinin (HA) peptide, the IN peptide, with anti-HA antibody was demonstrated using a field-effect transistor (FET) with an n-type silicon (Si) channel and a nickel (Ni) self-aligned silicide source/drain that was fabricated by a conventional top-down process. The specific binding of the IN peptide with anti-HA antibody in phosphate buffered saline (PBS) occurs on the patterned SiO2 surface through covalent linkage. Positive ions in the buffer create majority carriers in the n-type Si channel, leading to a rapid increase in current across that channel. However, specific binding of the negatively charged antigens on the SiO2 surface overlaying the Si channel results in the reduction of electrons induced in the Si channel by the positive ions, causing a significant decrease in the channel current. The settling time for obtaining a stable signal change, driven by the negatively charged antigens bound to antibody, extrapolates to approximately 32s. [doi:10.2320/matertrans.M2012068]

Nickel Silicide Formation Using Excimer Laser Annealing

In this work, we report on a self-aligned nickel silicide formation technique based on excimer laser annealing (ELA). We evaluate this process for the front contact formation of industrial PERC type solar cells on random pyramid textured Si surfaces where damage to surface texture, emitter passivation, or to the shallow junction should be avoided or minimized. PERC type solar cells obtained by POCl3 diffusion were processed on large area (12.5x12.5cm2) CZ-Si. Self-aligned litho-free Ni/Cu contacts defined by ps-laser ablation of the SiO2/SiNx anti-reflective coating (ARC) and subsequent ELA of the Ni layer were compared to conventional Ag screen printed contacts.The novel ELA process results in an absolute gain in Jsc of 0.8mA/cm2 as well as a drop of 0.3Ω.cm2 in series resistance (Rs) compared to SP Ag contacts due to reduced shading and resistance losses. This leads to 0.5% absolute increase in efficiency from 19.3% to 19.7% since other characteristics (Voc, pFF) could be maintained to the same level. In this work, the best performing cell with the ELA process reached an outstanding 20.0% energy conversion efficiency with Jsc=39.3mA/cm2, Voc=649.8mV, and FF=78.3%.

High performance poly-Si thin film transistors fabricated by self-aligned seed induced lateral crystallization

In this study, a low temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) was fabricated by self-aligned silicide seed induced lateral crystallization (SA-SILC). In comparison with a self-aligned metal induced lateral crystallization (SA-MILC) TFT, the SA-SILC TFT showed better electrical properties. In particular, the leakage current was decreased by SA-SILC at high drain voltages. It was found that the Ni rich phase between the channel and drain junction region acted as trapping sites to generate leakage current by thermionic field emission. After applying the SA-SILC process, the p-channel polycrystalline silicon (poly-Si) TFT exhibited a mobility of 67 cm 2/V·s, a minimum leakage current of 2.6 × 10−11 A at V D = −5 V, a subthreshold slope of 0.8 V/dec, and a maximum on/off ratio of 7.0 × 10 6, together resulting in a high-performance device that surpasses the conventional SA-MILC poly-Si TFT.

Theoretical investigation of silicide Schottky barrier detector integrated in horizontal metal-insulator-silicon-insulator-metal nanoplasmonic slot waveguide

An ultracompact integrated silicide Schottky barrier detector (SBD) is designed and theoretically investigated to electrically detect the surface plasmon polariton (SPP) propagating along horizontal metal-insulator-silicon-insulator-metal nanoplasmonic slot waveguides at the telecommunication wavelength of 1550 nm. An ultrathin silicide layer inserted between the silicon core and the insulator, which can be fabricated precisely using the well-developed self-aligned silicide process, absorbs the SPP power effectively if a suitable silicide is chosen. Moreover, the Schottky barrier height in the silicide-silicon-silicide configuration can be tuned substantially by the external voltage through the Schottky effect owing to the very narrow silicon core. For a TaSi(2) detector with optimized dimensions, numerical simulation predicts responsivity of ~0.07 A/W, speed of ~60 GHz, dark current of ~66 nA at room temperature, and minimum detectable power of ~-29 dBm. The design also suggests that the device's size can be reduced and the overall performances will be further improved if a silicide with smaller permittivity is used.

Simplified Model of the Effect of Source/Drain Doping Gradient on Capacitance and Resistance in a Double-Gate Metal–Oxide–Semiconductor Field-Effect Transistor

Simplified models of capacitance and resistance in the external region are presented and the mobility enhancement effect is verified for extremely scaled and undoped double-gate metal–oxide–semiconductor field-effect transistors (MOSFETs) with the raised source/drain and self-aligned silicide structure and different source/drain doping gradients. The accuracy and universality of these models were confirmed using a two-dimensional simulator. Results indicated that a 3 nm increment of the source/drain lateral doping straggle can reduce the intrinsic delay by about 30% and the leakage current by about 95%.

Silicon Carbide Vertical JFET with Self-Aligned Nickel Silicide Contacts

Trenched implanted vertical JFETs (TI-VJFETs) with self-aligned gate and source contacts were fabricated on commercial 4H-SiC epitaxial wafers. Gate regions were formed by aluminium implantation through the same silicon oxide mask which was used for etching mesa-structures. Self-aligned nickel silicide source and gate contacts were formed using a silicon oxide spacer formed on mesa-structure sidewalls by anisotropic thermal oxidation of silicon carbide followed by anisotropic reactive ion etching of oxide. Fabricated normally-on 4H-SiC TI-VJFETs demonstrated low gate leakage currents and blocking voltages exceeding 200 V.

Self-Aligned Silicidation of Surround Gate Vertical MOSFETs for Low Cost RF Applications

We report for the first time a CMOS-compatible silicidation technology for surround-gate vertical MOSFETs. The technology uses a double spacer comprising a polysilicon spacer for the surround gate and a nitride spacer for silicidation and is successfully integrated with a Fillet Local OXidation (FILOX) process, which thereby delivers low overlap capacitance and high-drive-current vertical devices. Silicided 80-nm vertical n-channel devices fabricated using 0.5-μm lithography are compared with nonsilicided devices. A source-drain (S/D) activation anneal of 30 s at 1100°C is shown to deliver a channel length of 80 nm, and the silicidation gives a 60% improvement in drive current in comparison with nonsilicided devices. The silicided devices exhibit a subthreshold slope (S) of 87 mV/dec and a drain-induced barrier lowering (DIBL) of 80 mV/V, compared with 86 mV/dec and 60 mV/V for nonsilicided devices. S-parameter measurements on the 80-nm vertical nMOS devices give an fT of 20 GHz, which is approximately two times higher than expected for comparable lateral MOSFETs fabricated using the same 0.5-μm lithography. Issues associated with silicidation down the pillar sidewall are investigated by reducing the activation anneal time to bring the silicided region closer to the p-n junction at the top of the pillar. In this situation, nonlinear transistor turn-on is observed in drain-on-top operation and dramatically degraded drive current in source-on-top operation. This behavior is interpreted using mixed-mode simulations, which show that a Schottky contact is formed around the perimeter of the pillar when the silicided contact penetrates too close to the top S/D junction down the side of the pillar.

Microcrystalline-Si thin-film transistors formed by using palladium silicided source/drain contact electrode

Microcrystalline-Si thin-film transistors (μC-Si TFTs) formed by using the source/drain contact electrode of self-aligned palladium silicide have been investigated. Both the self-aligned palladium silicided scheme and the previous top-gate staggered structure employ two-mask process steps for fabricating μC-Si TFTs. However, the self-aligned palladium silicided scheme would cause better device characteristics than the top-gate staggered structure, primarily due to more carrier tunneling. For a gate length of 2 μm, as compared to the top-gate staggered scheme, this silicided scheme can result in a 40% improvement of on-state current. In addition, as the gate length is reduced to 1 μm, considerable short-channel effect is caused for both the device schemes.

A study on selective etching for elevated PtSi salicide process and work function modulation of PtSi alloying with Hf

AbstractThe selective etching process for elevated self‐aligned silicide (salicide) utilizing PtSi has been investigated. We have developed a novel selective etching process utilizing dilute aqua regia followed by etching with dilute HF. It was found that the residual Pt‐rich silicide layers on the sidewall were successfully removed. We also investigated work function modulation of PtSi alloyed with Hf. The barrier height for electrons of PtSi was reduced approximately 0.1 eV for PtxHf1‐xSi formed by the silicidation of Pt (17 nm)/Hf (4 nm)/Si (100) stacked layer structures. © 2010 Wiley Periodicals, Inc. Electron Comm Jpn, 93(8): 32–37, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecj.10215

Enhanced growth of low-resistivity titanium silicides on epitaxial Si 0.7Ge 0.3 on (001)Si with a sacrificial amorphous Si interlayer

Enhanced growth of low-resistivity self-aligned titanium silicides on epitaxial Si 0.7Ge 0.3 with a sacrificial amorphous Si (a-Si) interlayer has been achieved. The a-Si layer with appropriate thickness was found to prevent Ge segregation, decrease the growth temperature, as well as maintain the interface flatness and morphological stability in forming low-resistivity C54-TiSi 2 on Si 0.7Ge 0.3 grown by molecular beam epitaxy. The process promises to be applicable to the fabrication of high-speed Si–Ge devices.

Optical metrology of Ni and NiSi thin films used in the self-aligned silicidation process

The thickness-dependent optical properties of nickel metal and nickel monosilicide (NiSi) thin films, used for self-aligned silicidation process, were characterized using spectroscopic ellipsometry. The thickness-dependent complex dielectric function of nickel metal films is shown to be correlated with the change in Drude free electron relaxation time. The change in relaxation time can be traced to the change in grain boundary (GB) reflection coefficient and grain size. A resistivity based model was used as the complementary method to the thickness-dependent optical model to trace the change in GB reflection coefficient and grain size. After silicidation, the complex dielectric function of NiSi films exhibit non-Drude behavior due to superimposition of interband absorptions arising at lower frequencies. The Optical models of the complete film stack were refined using x-ray photoelectron spectroscopy, Rutherford backscattered spectroscopy, and x-ray reflectivity (XRR).

Optimum location of silicide/Si interface in ultra-thin body SOI MOSFETs with recessed and elevated silicide source/drain contact structure

Optimization of the series resistance of silicide contact structure in ultra-thin body (UTB) silicon-on-insulator (SOI) MOSFET with elevated source/drain (S/D) is examined through theoretical analysis and 2-dimensional simulation. It is found that the optimum silicide/Si interface position, which exhibits lowest parasitic series resistance, can be located at inside of SOI layer under the surface as the effective contact length is scaled down further below 100 nm regime. The closed-form analytical expressions derived from modified transmission line model principle provide a guideline for optimum design of silicide thickness and contact parameters in self-aligned silicide technology.

Anomalous Nickel Silicide Encroachment in n-Channel Metal–Oxide–Semiconductor Field-Effect Transitors on Si(110) Substrates and Its Suppression by Si+ Ion-Implantation Technique

A novel low-leakage-current nickel self-aligned-silicide (SALICIDE) process in n-channel metal–oxide–semiconductor field-effect transistors (nMOSFETs) on Si(110) substrates is reported. Anomalous nickel silicide encroachment in the <110> direction in nMOSFETs on Si(110) substrates is found for the first time. This encroachment causes anomalous off-state leakage current (Ioff) in nMOSFETs on Si(110) substrates. In particular, in the case of the <110> channel on Si(110) substrates, Ni atoms easily diffuse in the <110> direction, and nickel silicide preferentially grows in the <110> direction. As a result, anomalous leakage current between the drain and the source occurs, and the leakage current seriously degrades transistor performance. In order to overcome these problems, we propose a method of suppressing anomalous Ioff on Si(110) substrates by Si+ ion-implantation technique prior to the nickel SALICIDE process. This method is effective for suppressing the encroachment of nickel silicide and realizing low-leakage complementary metal–oxide–semiconductor (CMOS) devices on Si(110) substrates.

Advances on 45nm SiGe-Compatible NiPt Salicide Process

NiPt self-aligned silicide (salicide) has become a major candidate for the 45nm node due to its better thermal stability and the surface morphology of NiSi on Si substrate [1,2]. SiGe has been proposed for PMOS strain engineering [3]. The relevant SiGe oxidation behavior [4], reaction with platinum [5] and thermal stress behavior [6] are important factors in developing a process for 45nm NiPt salicide over SiGe stressor. These concerns require the review of the current process for NiPt to verify its compatibility and extendibility.

1.88-$\hbox{m}\Omega\cdot\hbox{cm}^{2}$ 1650-V Normally on 4H-SiC TI-VJFET

The SiC trenched-and-implanted vertical junction field-effect transistor (TI-VJFET) is an excellent device for power switching applications, but its on-resistance needs to be further reduced to suppress ON-state power loss. In this paper, we used small cell pitch size and high channel/drift layer doping concentration to achieve low on-resistance. Advanced fabrication processes, such as Bosch process trench etching, self-aligned Ni silicide, and self-aligned gate overlay were implemented to support such an aggressive design. Normally on 4H-SiC TI-VJFETs of various channel-opening dimensions have been designed and fabricated based on a 12 mum, 1.8 times 1016 cm-3 doped drift layer. Record high performance TI-VJFETs have been achieved and will be reported. Other SiC VJFET structures under active research are reviewed and compared to TI-VJFET. Without the need for epi-regrowth or stringent lithography alignment, TI-VJFET has the advantage of a less demanding fabrication process. In addition, its high current density, adjustable channel width and low gate resistance make TI-VJFET an excellent device for fast power switching applications.

Two-Mask Silicides Fully Self-Aligned for Trench Gate Power IGBTs With Superjunction Structure

We present a new trench gate power IGBT with superjunction structures in its drift region, which exhibits a strongly improved relationship between blocking voltage and on-resistance. An accurate control of the impurity concentration of the n drift region in the trench sidewall is important in achieving the performance of the proposed IGBT, and angle ion implantation is considered to be the most suitable method for its fine controllability; therefore, we optimized the trench sidewall doping by adjusting the implanted ion dosage and incident angles. In addition, source and gate contacts are realized by self-aligned silicides technology; therefore, the devices are made fully self-aligned with two masks - one for trench and another for source and body doping selection. The output <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> characteristics and threshold voltage are measured after the devices were fabricated.

Top-Gate Amorphous Silicon TFT With Self-Aligned Silicide Source/Drain and High Mobility

We report a process for top-gate amorphous silicon thin-film transistors (alpha-Si TFTs) that employs a self-aligned metal silicide for source and drain (S/D). All process steps, including deposition of active layers and formation of metal silicide, are accomplished at temperatures that are less than or equal to 280degC. The thermal budget is compatible with flexible polymer substrates. The fabricated devices exhibit threshold voltages of ~2.7 V, saturation electron field-effect mobility of 1.0 cm2/V ldr s, subthreshold slope of 600 mV/dec, and on/off ratio of ~2 times 106. These top-gate alpha-Si TFTs with self-aligned silicide S/D have dc performance that is comparable to that of conventional bottom-gate alpha-Si TFTs. Our results suggest that the top-gate alpha-Si TFT geometry merits reevaluation for industrial use.

A Study on Selective Etching for Elevated PtSi Salicide Process and Work Function Modulation of PtSi Alloying with Hf

The selective etching process for elevated self-aligned silicide (salicide) utilizing PtSi has been investigated. We have developed novel selective etching process utilizing a diluted aqua regia followed by a diluted HF light etching. It was found that the residual Pt-rich silicide layers on the sidewall have been successfully removed. We have also investigated a work function modulation of PtSi alloying with Hf. The barrier height for electron of PtSi has been reduced approximately 0.1 eV for PtxHf1-xSi formed by the silicidation of Pt(17 nm)/Hf(4 nm)/Si(100) stacked layer structures.

Post Salicidation Clean: Selective Removal of Un-Reacted NiPt Towards NiPtSi(Ge)

Ni(alloy) silicides have recently gained much attention due to their improved properties. Ni(Pt)Si has indeed become one of most promising candidates to replace NiSi as contact electrodes. To avoid bridging at the spacers and the isolation areas, after self-aligned silicidation (salicidation), un-reacted NiPt needs to be removed. This post salicidation clean process has to be selective towards all possibly exposed materials such as Si3N4 (spacers), SiO2 (field oxide), NiPtSi (contact and gate electrodes), and NiPtSiGe (contact electrodes of source/drain for strain applications). In this work, it is found that dilute HCl/HNO3 mixtures can well be used for NiPt post salicidation clean. It is shown that this process has a high etch rate for NiPt and a high selectivity towards other possibly exposed materials. Furthermore, the sheet resistance and the thickness of the silicides after this selective etch are well within specification providing a clean, environmentally-friendly process with low cost-of-ownership.