Self-aligned Silicide Research Articles

Optimization of Ti and Co Self-Aligned Silicide RTP for 0.10 μm Cmos

ABSTRACTAs CMOS technologies are scaled to 0.10 μm and beyond, self-aligned silicide (salicide) processes find difficult challenges. As junction depths and linewidths are scaled, achieving both low sheet resistance and low contact resistance maintaining low diode leakage becomes increasingly difficult. In this paper we present studies of Ti and Co salicide processes implemented into a 0.10 μm CMOS technology. We show that both for Ti and Co, the optimization of RTP parameters plays a crucial roll in achieving a successful implementation. For Co salicide, optimization of RTP conditions results in elimination of shallow junction leakage (its main scaling problem). Two-step RTP and one-step RTP Ti salicide processes are compared, showing the advantages of one-step RTP. The RTP process windows for low resistance narrow gates (the main scaling issue for Ti salicide) are analyzed. Processes with pre-amorphization, with Mo doping and with a combination of both are compared. An optimal process using Mo and preamorphization implants and one-step RTP is shown to result in excellent device characteristics and low resistance to 0.06 μm gates.

Optimization of Ti and Co Self-Aligned Silicide RTP for 0.10 μm CMOS

ABSTRACTAs CMOS technologies are scaled to 0.10 μm and beyond, self-aligned silicide (salicide) processes find difficult challenges. As junction depths and linewidths are scaled, achieving both low sheet resistance and low contact resistance maintaining low diode leakage becomes increasingly difficult. In this paper we present studies of Ti and Co salicide processes implemented into a 0.10 μm CMOS technology. We show that both for Ti and Co, the optimization of RTP parameters plays a crucial roll in achieving a successful implementation. For Co salicide, optimization of RTP conditions results in elimination of shallow junction leakage (its main scaling problem). Two-step RTP and one-step RTP Ti salicide processes are compared, showing the advantages of one-step RTP. The RTP process windows for low resistance narrow gates (the main scaling issue for Ti salicide) are analyzed. Processes with pre-amorphization, with Mo doping and with a combination of both are compared. An optimal process using Mo and preamorphization implants and one-step RTP is shown to result in excellent device characteristics and low resistance to 0.06 μm gates.

Growth and Characterization of Self-Aligned Erbium Silicide on N-Type, (100) Oriented Silicon

ABSTRACTIn view of its low barrier height to n-type Si, ErSi2 has potential applications as an infrared detector, as low-resistance ohmic contacts and as source/drain regions in Schottky barrier MOSFETs. Although there is a substantial body of work on ErSi2 grown on Si(111), there are relatively few published papers on the growth and properties of ErSi2 on Si(100). In order to develop a CMOS-compatible process, we have studied the growth of ErSi2 using a multi-source, UHV magnetron system to sputter-deposit 20 nm Ti/(10–50) nm Er bilayers on chemically cleaned n-Si(100) substrates followed by ex-situ rapid thermal annealing in N2. Highly oriented ErSi2 in the hexagonal phase was formed at an annealing temperature of 400°C with ErSi2 (100) Si(100). The Ti overlayer and the unreacted Er were selectively etched in HF and HNO3, respectively, leaving behind an ErSi2 layer with a smooth surface morphology, a uniform bulk composition and a planar ErSi2/Si interface. Results of electrical sheet resistance and Schottky barrier height measurements on these layers will be reported.

New Ti-SALICIDE process using Sb and Ge preamorphization for sub-0.2 μm CMOS technology

A new process for thin titanium self-aligned silicide (Ti-SALICIDE) on narrow n/sup +/ poly-Si lines and n/sup +/ diffusion layers using preamorphization implantation (PAI) with heavy ions of antimony (Sb) and germanium (Ge) has been demonstrated for application to 0.2-/spl mu/m CMOS devices and beyond. Preamorphization enhances the phase transformation from C/sub 49/Ti/sub x/Si/sub x/ to C/sub 54/TiSi/sub 2/ and lowers the transformation temperature by 80/spl deg/C so that it occurs before conglomeration in narrow lines. Preamorphization by Sb and Ge implantation yields better results than that by As. The sheet resistance of TiSi/sub 2/ on heavily As doped poly-Si lines are 3.7 /spl Omega///spl square/ and 3.8 /spl Omega///spl square/ for the samples preamorphized by Ge and Sb implantations even with line width down to 0.2 /spl mu/m. There is less leakage in the Ti-SALICIDE diode with preamorphization than without it. The probable reasons and mechanisms are discussed.

Self-Aligned Gate Metallization Processes with Low-Thermal Budget

ABSTRACTA novel concept for CMOS transistor gate metallization is described. It is featured with Gate Cloisonné, a process consisting of dielectric deposition over frontend transistors, followed by chemical mechanical polishing to re-expose the gate pattern on a planar dielectric background. Based on this concept, two metallization schemes have been developed. One is self-aligned metal gate process, which allows for low thermal budget gate metallization with element metals such as W and Al, resulting in a very low sheet resistance (< 1 Ω/sq). The other scheme is dual self-aligned silicidation, which enables decoupling of gate silicidation from that of source/drain silicon areas. Titanium based silicidation process is implemented to form thick silicide on narrow polysilicon gates and thin one over active silicon areas. Low gate sheet resistance (≈ 1.9Ω/sq) is achieved with complete suppression of linewidth effects. Both the metallization schemes are a priori scaleable to deep submicron technologies and suitable to fabricating ultra-shallow junction devices with very low gate sheet resistance. Both of them have been implemented in a 0.25-μm CMOS technology.

Integration of NiSi SALICIDE for Deep Submicron CMOS Technologies

ABSTRACTA NiSi-based self-aligned silicidation (SALICIDE) process has been integrated into a 0.25 Ion CMOS technology. It involves rapid thermal annealing (RTA) of Ni thin films (300, Å thick) on Si substrates in the temperature range ≈400 - 700 °C. It was found that the NiSi sheet resistance (Rs) gradually decreases with decreasing linewidth. Parameters, such as RTA temperature, substrate dopant (As vs BF2) and structure (single crystal vs poly), were found to have little effects on Rs. NiSi forms a smoother interface with single crystalSi than with poly Si, and has a slightly lower resistivity. MOSFETs based on NiSi show comparable device characteristics to those obtained with Ti SALICIDE. Upon thermal annealing, NiSi remains stable at 450 °C for more than 39 hours. The same is true for 500 °C anneals up to 6 hours, except for NiSi narrow lines (<0.5 μm) on n+ poly Si substrates whose Rs is moderately increased after a 6 hr anneal. This work demonstrates that with an appropriate low-thermal budget backend process, NiSi SALICIDE can be a viable process for deep submicron ULSI technologies.

A self-aligned silicide technology with the Mo/Ti bilayer system

A self-aligned silicide technology using a bilayer of 60 nm Ti and 0.5 nm Mo deposited on blank and patterned silicon substrates was investigated. As a consequence of the direct formation of the C54 phase titanium silicide, a lower sheet resistance was always measured on narrow Si lines with the presence of the thin Mo interposing layer than without Mo, under otherwise the same conditions for silicidation. With Mo, the sheet resistance of the silicide formed on the patterned wafers was also much less sensitive to the Si linewidth. Moreover, the standard deviation in the sheet resistance across the wafer was found to be considerably smaller for the silicide formed with presence of Mo in comparison to reference sample. The presence of Mo at the TiSi interface only slightly increases the contact resistance between the silicide formed on the p + or n + silicon substrates. Thus, using the Mo/Ti bilayer to replace Ti appears to be very promising for sub-micron applications, as the deposition of Mo can easily be integrated into the standard process.

Structural investigation of self-aligned silicidation on separation by implantation oxygen

Self-aligned silicidation is a well-known process to reduce the source, drain, and gate parasitic resistances of submicron metal-oxide-semiconductor devices. This process is particularly useful for devices built on very thin Si layer (∼1000 Å or less) on insulators. Since the amount of Si available for silicidation is limited by the thickness of the Si layer, once the Si in the source and drain region is fully consumed during silicidation, excessive silicide formation could lead to void formation near the silicide/silicon interface beneath the oxide edge. In this article, we study the effects of different metals (Ti, Ni, Co, and Co/Ti bilayer) with varying thickness on the formation of voids. A change in the moving species during lateral silicide formation was found to be the likely cause for the voids, even if the metals are the moving species during silicidation in the thin film case.

Salicidation process using NiSi and its device application

Self-aligned silicidation is a well-known process to reduce source, drain, and gate resistances of submicron metal-oxide-semiconductor devices. This process is particularly useful for devices built on very thin Si layers (∼1000 Å or less) on insulators because of the large source and drain resistances associated with the thin Si layer. NiSi is a good candidate for salicidation process due to its low resistivity, low formation temperature, little silicon consumption, and large stable processing temperature window. In this article, the formation of nickel mono-silicide (NiSi) using rapid thermal annealing, the thermal stability of NiSi on n+ poly-Si and the contact resistance of NiSi on n+ Si layers in a SIMOX structure were investigated. NiSi salicidation process was, then, incorporated into a NMOS/SIMOX device fabrication for partial and full consumption of the Si in the source and drain regions during the salicidation process. The effects of void formation and silicide encroachment on the device performance were also studied.

Agglomeration Resistant Self-Aligned Silicide Process Using N 2 Implantation into TiSi 2

An agglomeration resistant self-aligned silicide (SALICIDE) process using N2 implantation into TiSi2 films has been developed. The film morphology and the film sheet resistance after high-temperature annealing in an Ar ambient were evaluated as a function of implanted nitrogen doses. High implantation doses of 5×1016 cm-2 or more realized the completely flat film after the annealing; however there is an optimum dose of approximately 1×1016 cm-2 for maintaining the film sheet resistance at its minimum value. This phenomenon could be explained by the fact that the main composition of the film was changed from TiSi2 (C54) to TiN with a 5×1016 cm-2 or more nitrogen implantation and that the TiN film contains Si crystals. A successful application of this technique to a 0.8 µm n-MOS transistor is also presented.

XAFS Studies of Self-Aligned Platinum Silicide Thin Films at the Pt M3,2Edge and the Si K-Edge

Pt-Si thin films with the thickness of several hundred A prepared on n-type Si(100) by UHV sputter-deposition procedures and subsequent annealing have been studied with X-ray absorption fine structure spectroscopy at the Pt M 3,2 edge and the Si K-edge. It is found that. under favourable conditions. single phase PtSi films can be obtained. These films exhibit the same XAFS characteristics as those of bulk samples. The M 3,2 edge exhibits XANES features very similarto those of the Pt L, 3.2 edge obtained front the samples. The analysis of the Pt M 3.2 edge whiteline and the Si K-edge results show significant charge redistribution at both Pt and Si sites upon silicidation.

Materials for VLSI Processes

Present status and future trends in materials for some critical areas of VLSI have been presented. The choice of starting substrate in terms of epi, larger diameter and Silicon On Insulator(SOI) wafer has been described. Issues related to Self Aligned Silicide(SALICIDE) and barrier metal have been discussed. Importance of selection of materials for interconnect technology has been highlighted. Also planarization techniques and materials for contact and via fill have been described.

Study on titanium salicide process for thin-film SOI devices

TFSOI (Thin-Film Silicon-On-Insulator) technology has made significant progress recently. In this work, the titanium SALICIDE (Self-Aligned siLICIDE) process has been studied, optimized and applied on a CMOS-compatible TFSOI technology for low-voltage, low-power microwave applications. The gate sheet resistance and total source/drain series resistance of a TFSOI NMOSFET with a 80 nm thick active silicon layer are 6.2 Ω/square and 700 Ω.μm, respectively, with a 30 nm thick titanium disilicide on both the gate and source/drain areas. The maximum oscillation frequency, f max, of a 0.75 μm TFSOI NMOSFET fabricated with this technology is equal to 11 GHz for a supply voltage of 0.9 V.

Materials aspects of Ti and Co silicidation of narrow polysilicon lines

The scalability of Ti and Co self-aligned silicide processes to deep-submicrometer technologies is determined by the fundamental materials aspects controlling phase formation and evolution. The kinetics of the high resistivity phase to low resistivity phase transformation (TiSi 2 C49 to C54 transformation for Ti, and CoSi to CoSi 2 transformation for Co) were studied for films on deep-submicrometer n + gates. For TiSi 2, results of a detailed Johnson-Mehl-Avrami analysis show that activation energies for the transformation increase with decreasing film thickness in the 28–64 nm range and are insensitive to linewidth in the 0.26-0.8 μm range, while transformation times increase as the linewidth or film thickness decreases. For Co, the transformation is diffusion limited, whih the square of CoSi 2 film thickness depending linearly on time. The transformation rate is also observed to be linewidth dependent, while the activation energy is quite insensitive to linewidth. The Co silicide phase tranformation proceeds faster than the Ti silicide phase transformation at low temperatures, resulting in a range of process parameters for which no linewidth dependence is observed for Co silicide and a strong linewidth dependence is observed for Ti silicide owing to incomplete phase transformation of the narrowest lines.

Texture of titanium self-aligned silicide (salicide)

The conventional self-aligned silicide (salicide) in IC manufacturing is made by depositing a thin (10--50 nm) titanium film on silicon wafer by physical vapor deposition (PVD) plus two rapid thermal annealing (RTA) to induce reaction between titanium and substrate. To make a via plug titanium nitride and aluminum alloy are deposited successively on the top of salicide to draw the electric current out of source or drain to interconnects. The reliability of a TiSi{sub 2}-TiN-Al tri-layer is an important issue. In particular the electromigration resistance of the aluminum alloy is heavily effected by its texture. Since the top layer nucleates on the under layer the texture of latter might influence that of the former. Therefore the texture of the aluminum alloy is expected to be correlated with that of the underlying silicide. Then, for the reliability of devices using salicide, the study of silicides` texture seems relevant to process control in wafer fabrication.

Self-aligned cobalt disilicide/silicon Schottky barrier contacts: fabrication, materials and electrical characterization

Polycrystalline cobalt disilicide films have been formed successfully on n-type (100)- and (111)-oriented silicon substrates using a relatively low technology route involving cobalt metal evaporation and a rapid thermal annealing procedure. The same procedure has been used to fabricate Schottky barrier contacts using a self-aligned silicide process. The properties of the reacted overlayers and interfaces have been examined using nuclear reaction analysis, Rutherford backscattering spectrometry, cross-sectional transmission electron microscopy, sheet resistance, I - V and C - V measurements. Examination of the contacts using optical microscopy revealed lateral silicide overgrowth which has been explained by consideration of the known growth kinetics. These results lead to explanations for non-idealities in the electrical characteristics which show ideality factors as low as 1.03 and barrier heights typically of 0.65 eV.

Polysilicon Thin Film Transistors with Cobalt amd Nickel Silicide Source and Drain Contacts

AbstractPolysilicon n-type thin film transistors have been fabricated with self-aligned cobalt and nickel silicide contacts to the source and drain regions. The sheet resistance of the source and drain without silicide is above 200 Ω/‪. The cobalt and nickel silicide films have sheet resistance below 30 Ω/‪. The contact resistance of the silicided devices is also much lower. The reduced extrinsic resistance is shown to improve the current in the “on” state, without increasing the leakage current. This study includes examination of cobalt and nickel silicidation on thin polysilicon films at temperatures compatible with polysilicon TFT-LCD processes.

In Situ Rapid Thermal Hydrogenation Pretreatment of Ti for Salicide RTA

AbstractAn in situ rapid thermal hydrogenation (RTH) pretreatment of titanium prior to rapid thermal annealing (RTA), or RTH/RTA, is proposed as a silicide formation annealing in a CMOS self-aligned silicide (salicide) process. The in situ RTH is found to enhance silicidation, to reduce nitridation, and even to lower the resultant sheet resistance of titanium silicide.During in situ RTH (e.g., at 550°C), amorphous Ti silicide (e.g., 15-nm thick) grows selectively on Si. Furthermore, Ti nitridation during subsequent RTA (690°C, N2, 10 Torr, 30 s) is reduced depending on RTH (H2, 10 Torr, 30 s) temperature. Accordingly, for 550°C RTH and an initial Ti thickness of 15 nm, the sheet resistance obtained at the 0.27-μm-wide n+ poly-Si gate after a phase transition annealing (800°C, Ar, 10 s) was lower (11.7 Ω /□, st. dev. = 6%) than that of conventional Ti silicide (15.8 Ω/□, st. dev. = 10%). The silicidation enhancement and nitridation reduction are related to crystal structure metamorphosis or to hydrogen interstitial incorporation in the Ti layer during RTH as observed by x-ray diffraction analysis. It is concluded that in situ RTH pretreatment before RTA is very promising as a sub-quarter-micron CMOS salicide process.

One micrometre scale self-aligned cobalt disilicideSchottky barrierdiodes

CoSi2/n-type silicon (111) Schottky barrier diodes on a 1 µm scale have been fabricated using a self-aligned silicide process incorporating magnetron sputtering and rapid thermal processing, in an industrial environment. Anneal temperatures in the range 700–1100°C have been used, and ideality factors of 1.06–1.07 were obtained in the range 700–900°C with larger values for higher temperatures. The consistency in the values of the ideality factor indicates that a wide annealing temperature window exists for the successful fabrication of CoSi2/silicon diodes.

A comparison of C54-TiSi2 formation in blanket and submicron gate structures using in situ x-ray diffraction during rapid thermal annealing

We demonstrate the use of a synchrotron radiation source for in situ x-ray diffraction analysis during rapid thermal annealing (RTA) of 0.35 μm Salicide (self-aligned silicide) and 0.4 μm Polycide (silicided polysilicon) TiSi2 Complementary Metal Oxide Semiconductor (CMOS) gate structures. It is shown that the transformation from the C49 to C54 phase of TiSi2 occurs at higher temperatures in submicron gate structures than in unpatterned blanket films. In addition, the C54 that forms in submicron structures is (040) oriented, while the C54 that forms in unpatterned Salicide films is randomly oriented. Although the preferred oreintation of the initial C49 phase was different in the Salicide and Polycide gate structures, the final orientation of the C54 phase formed was the same. An incomplete conversion of C49 into C54-TiSi2 during the RTA of Polycide gate structures was observed and is attributed to the retarding effects of phosphorus on the transition.