Self-aligned Heterojunction Bipolar Transistor Research Articles

High-performance self-aligned SiGeC HBT with selectively grown Si/sub 1-x-yGe/sub x/C/sub y/ base by UHV/CVD

Si/sub 1-x-y/Ge/sub x/C/sub y/ selective epitaxial growth (SEG) was performed by cold-wall, ultrahigh-vacuum chemical vapor deposition, and the effects of incorporating C on the crystallinity of Si/sub 1-x-y/Ge/sub x/C/sub y/ layers and the performance of a self-aligned SiGeC heterojunction bipolar transistor (HBT) were evaluated. A Si/sub 1-x-y/Ge/sub x/C/sub y/ layer with good crystallinity was obtained by optimizing the growth conditions. Device performance was significantly improved by incorporating C, as a result of applying Si/sub 1-x-y/Ge/sub x/C/sub y/ SEG to form the base of a self-aligned HBT. Fluctuations in device performance were suppressed by alleviating the lattice strain. Furthermore, since the B out diffusion could be suppressed by incorporating C, the cutoff frequency was able to be increased with almost the same base resistance. A maximum oscillation frequency of 174 GHz and an emitter coupled logic gate-delay time of 5.65 ps were obtained at a C content of 0.4%, which shows promise for future ultrahigh-speed communication systems.

Si-Ge-H-Cl 계를 이용한 자기정렬 HBT용 Si 및 SiGe의 선택적 에피성장

Low temperature selective epitaxial growth of Si and SiGe has been obtained using an industrial single wafer chemical vapor deposition module operating at reduced pressure. Epitaxial Si and heteroepitaxial SiGe deposition with Ge content about 20 % has been studied as extrinsic base for self-aligned heterojunction bipolar transistors(HBTs), which helps to reduce the parasitic resistance to obtain higher maximum oscillation frequencies(f<TEX>$\_$</TEX>max/). The dependence of Si and SiGe deposition rates on exposed windows and their evolution with the addition of HCl to the gas mixture are investigated. SiH<TEX>$_2$</TEX>Cl<TEX>$_2$</TEX> was used as the source of Si SEG(Selective Epitaxial Growth) and GeH<TEX>$_4$</TEX> was added to grow SiGe SEG. The addition of HCl into the gas mixture allows increasing an incubation time even low growth temperature of 675∼725<TEX>$^{\circ}C$</TEX>. In addition, the selectivity is enhanced for the SiGe alloy and it was proposed that the incubation time for the polycrystalline deposit on the oxide is increased probably due to GeO formation. On the other hand, when only SiGe SEG(Selective Epitaxial Growth) layer is used for extrinsic base, it shows a higher sheet resistance with Ti-silicide because of Ge segregation to the interface, but in case of Si or Si/SiGe SEG layer, the sheet resistance is decreased up to 70 %.

High‐speed self‐aligned SiGe HBT and application to optical‐fiber‐link ICs

AbstractSiGe base heterojunction bipolar transistor (HBT) has high‐frequency and high‐speed performance comparable to compound semiconductor devices, and also has high cost because the existing Si process is used. Hence, this HBT is expected to be a key device for high‐speed optical transmission systems and microwave/millimeter‐wave wireless systems. The self‐aligned SiGe HBT developed here has a PASS structure with selective epitaxial growth by UHV/CVD and buffered polycrystalline Si in the lower layer of the external base polycrystalline Si. In this way, high‐speed operation of the intrinsic transistor and reduction of the parasitic capacitance and resistance are realized at the same time. The cutoff frequency and maximum oscillation frequency of this SiGe HBT are 122 and 163 GHz, and the gate delay time of the ECL circuit is an extremely fast 5.5 ps. Further, an IC to form a 40 Gbit/s optical receiver is fabricated. A preamplifier with a 45‐GHz bandwidth, a limit amplifier with a gain of 32 dB, a frequency divider of 60‐GHz operations, and a 1:4 DEMUX with a decision circuit operating at 40 Gbit/s are realized. It is shown that the 40 Gbit/s optical receiver IC chip set with the present SiGe HBTs reached a practical level. © 2002 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 85(7): 66–76, 2002; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjb.10004

Experimental procedure for the evaluation of GaAs-based HBT's reliability

This work describes the implementation of an experimental procedure to evaluate the reliability of Heterojunction Bipolar Transistors (HBT) on a GaAs substrate. It is based on the separation of aging test accelerating factors applied on two test vehicles: HBT and Transmission Line Model (TLM) structures associated with emitter, base and collector layers. To identify the physical origin of the degradation mechanism, analysis techniques are used: EDX, SEM and TEM observations for which a new sample preparation method has been worked out. Three different technological fabrication processes, are investigated: AlGaAs/GaAs double-mesa HBT, GaInP/GaAs self-aligned HBT and GaInP/GaAs fully planar HBT. These investigations have revealed two major failure mechanisms: the degradation of SiN–GaAs interface correlated with the increase of emitter-to-base leakage current of HBT submitted to combined bias and temperature stresses; the detachment of Ge/Mo/W emitter ohmic contact related to the base and collector current decrease for high level injection in forward regime. A 2D simulation has lead to modify the interface electrical properties to evaluate the impact of the two degradations on HBT dc characteristics.

Reliability investigation of InGaP/GaAs HBTs under current and temperature stress

The reliability of InGaP/GaAs N–p–n heterojunction bipolar transistors (HBTs) with different base metal contact systems (Au/Zn/Au, Ti/Au, Ti/Pt/Au and the novel Ti/ZrB 2/Au) under current and temperature stress is studied in this paper. We further report results of current stress on three p-GaAs doping impurities namely Zn, Be and C. The effect of O +/H + and O +/He + ions, used in the fabrication of planar self-aligned HBTs, is also investigated in the stability of device dc current gain. The instability phenomena typical of each factors and their effects on the HBT characteristics are reported.

New self-aligned processes for III–V electronic high speed devices

We report on two new self-aligned processes intended for microelectronic devices realization exhibiting a significant reduction of the number of elementary technological levels. These processes allow to obtain a very short self-aligned contact separation without using spacers or wet etched mesa overhangs. As an example, only three lithographic masks are used to realize a triple mesa self-aligned heterojunction bipolar transistor (HBT). A bilayer resist process is used to define the specific shape of the upper contact that is used for self-alignment. A combination of selective, isotropic, or anisotropic processes and very simple selective lift-off processes are used to define the mesa and the contacts which are also used as masks during etching. The alloying of contacts may be performed just after deposition and lift-off. These processes can reduce the production cost and increase the reliability for integration in comparison with conventional self-alignment using the selective wet etched emitter overhang in the HBT application. Furthermore, the parasitic access resistance can be reduced both by using thin mesa active layers and decreasing the contacts separation. This separation length can be determined by the aspect ratio of the bilayer resist, the characteristics, and parameters of the contact deposition equipment. At last, low induced damage inductively coupled plasma dry etch processes are partly used to reduce the dry etch damages. © 1999 American Vacuum Society.

Selective and non-selective growth of self-aligned SiGe HBT structures by LPCVD epitaxy

Silicon-germanium (SiGe) heterojunction bipolar transistors (HBT) have become increasingly important for high speed applications. Novel device structures are often required to fully exploit the advantages from incorporation of a heterojunction. In this work, a growth technique is described which uses both selective and non-selective growth of Si and SiGe to produce an advanced SiGe HBT structure. The surface morphology of the material grown is examined using Nomarski contrast optical microscopy and scanning electron microscopy (SEM), and the surface of the epitaxial areas appears smooth with a low defect density. The growth surface is reasonably planar, as needed for further device processing, which suggests the required thicknesses of both selective and non-selective epitaxy were achieved. The Ge and B profiles of the material are measured using secondary ion mass spectroscopy (SIMS), and the layer thicknesses are found to meet the device specification. The crystallinity and defects in the material are examined by transmission electron microscopy (TEM). The material produced is shown to be suitable for fabrication into the proposed device.

Submicron self-aligned HBT's by selective emitter regrowth

Fabrication of fully self-aligned heterojunction bipolar transistors (HBTs) by selective emitter regrowth is described. Scaled devices with emitter dimensions as small as 0.4/spl times/7 /spl mu/m/sup 2/ demonstrate current gain up to 29, with successful suppression of surface recombination effects. The RF characteristics of a 1.4/spl times/11 /spl mu/m/sup 2/ device exhibited f/sub T/ and f/sub MAX/ of 75 and 46 GHz, respectively, and is limited by the refractory base metallization. This technology is promising for scaled HBT applications where high-speed and low-power dissipation are critical.

Submicron, fully self-aligned HBT with an emitter geometry of 0.3 μm

A new fully self-aligned heterojunction bipolar transistor (HBT) process has been developed to fabricate submicron emitter geometries for applications requiring ultra low-power consumption and very high-speed performance. In this novel process approach the emitter, base and collector ohmic contacts are all self-aligned to the emitter mesa. Furthermore, the three ohmic contacts, i.e., emitter, base, and collector are defined and deposited in a single metalization step thereby simplifying the fabrication process. Using this new process we have fabricated HBT emitter geometries as small as 0.3 /spl mu/m/sup 2/ with RF performance of over 130 GHz. To our knowledge, this is the smallest HBT ever reported.

Precise etch stop for emitter etching of self-aligned heterojunction bipolar transistors

Dry etching of the AlInAs/GaInAs heterostructure for self-aligned heterojunction bipolar transistors was performed in a Cl 2/Ar plasma generated with an electron cyclotron resonance source. Optical emission spectroscopy was used to monitor the Ga emission intensity at 417.2 nm for endpoint detection in order to overcome nonselective etching between AlInAs and GaInAs as well as run-to-run variations in etch rate. The etching of the AlInAs emitter layer was stopped at different overetch times after the increase in the Ga intensity was detected. Ex situ surface analysis was used to characterize the surface after etching. X-ray photoelectron spectroscopy showed that both Al and Ga were present on the surface when overetching 3 s. No Al was detected for the 6 s overetch time, indicating that the AlInAs layer was completely removed. The specific contact resistivity (ρ c) at the etched surface was evaluated using transmission line measurements. As the overetch time increased from 3 to 6 s, ρ c decreased from 7.3 × 10 −4 to 4.1 × 10 −4 ω cm 2. This also indicates complete removal of the AlInAs emitter layer. Overetching of the GaInAs base layer should be limited for low base resistance to achieve better device performance. Therefore, reflectometry was used to measure the remaining thickness of GaInAs. For a 6 s overetch, less than 5 nm of the GaInAs base layer was removed and the AlInAs layer was completely etched. The surface morphology was also studied using atomic force microscopy. The root mean square surface roughness of 2.5 nm was obtained for the optimum overetch time. This was significantly lower than the value of 4.4 nm obtained after wet etching.

Integration of GalnP/GaAs heterojunction bipolar transistors and high electron mobility transistors

Integration of carbon-doped GaInP/GaAs heterojunction bipolar transistors (HBTs) and high electron mobility transistors (HEMTs) is demonstrated by growing an HBT on the top of a HEMT. A current gain of 60, a cutoff frequency of 59 GHz and a maximum oscillation frequency of 68 GHz were obtained for a 5×15 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> self-aligned HBT. The HEMT, with a gate length of 1.5 μm has a transconductance of 210 mS/mm, a cutoff frequency of 9 GHz and a maximum oscillation frequency of 22 GHz. It is shown that the GaInP/GaAs HBT on the HEMT is a simple Bi-FET technology suitable for microwave and mixed signal applications.

High frequency and low noise C-doped GaInP/GaAs heterojunction bipolar transistor grown by MOCVD using TBA and TBP

A C-doped GaInP/GaAs heterojunction bipolar transistor (HBT) grown by MOCVD using TBP and TBA is demonstrated. A current gain of 60, a cutoff frequency of 59 GHz, and a maximum oscillation frequency of 68 GHz were obtained for a 5 × 15 µm2 self-aligned HBT. A minimum noise figure of 1.4–2.6 was measured in the frequency range of 2–18 GHz. The results show that TBA and TBP are suitable MOCVD sources for growing high quality HBT materials.

Enhanced etch rates of tri-level resist stacks in microwave discharges

Thick (<or=4 mu m) tri-level resist schemes are increasingly common in processing of III-V devices such as heterojunction bipolar transistors (HBTS). Under the type of low-pressure, low-bias dry etching conditions necessary during processing of these damage-sensitive devices, conventional reactive ion etching produces impractically low etch rates. These etch rates can be substantially enhanced (sixfold) at the same pressure and bias by employing a hybrid microwave (2.45 GHz)-RF (13.56 MHz) reactor, which separates the control of the plasma density and the ion energies. Examples are given of the anisotropic etching of a tri-level resist scheme containing a PECVD SiNx transfer layer and a thick resist base layer, a typical scheme used in the processing of self-aligned HBTS.

High-low polysilicon-emitter SiGe-base bipolar transistors

Self-aligned heterojunction bipolar transistors with a high-low emitter profile consisting of a heavily doped polysilicon contact on top of a thin epitaxial emitter cap have been fabricated. The low doping in the single-crystal emitter cap allows a very high dopant concentration in the base with low emitter-base reverse leakage and low emitter-base capacitance. The thin emitter cap is contacted by heavily doped polysilicon to reduce the emitter resistance, the base current, and the emitter charge storage. A trapezoidal germanium profile in the base ensures a small base transit time and adequate current gain despite high base doping. The performance potential of this structure was simulated and demonstrated experimentally in transistors with near-ideal characteristics, very small reverse emitter-base leakage current, and 52-GHz peak f/sub max/, and in unloaded ECL and NTL ring oscillators with 24- and 19-ps gate delays, respectively. >

Monolithically integrated SQW laser and HBT laser driver via selective OMVPE regrowth

An AlGaAs/GaAs nan heterojunction bipolar transistor (HBT) laser driver circuit and a pseudomorphic InGaAs/GaAs/AlGaAs graded index single-quantum-well (SQW) laser have been laterally integrated to maintain surface planarity using selective organometallic vapor-phase epitaxy (OMVPE) regrowth of the HBT. The self-aligned HBTs exhibit a DC current gain of 30 and an f/sub t/ (f/sub max/) of 45(60) GHz. The 980-nm lasers exhibit room-temperature threshold current densities as low as 420

Surface passivation effects of As2S3 glass on self-aligned AlGaAs/GaAs heterojunction bipolar transistors

A recently developed As2S3 chemical treatment was used to passivate the perimeters of self-aligned heterojunction bipolar transistors (HBTs). The As2S3 chemical treatment significantly lowered the base current resulting in a two order of magnitude reduction in the collector current density at which dc current gain was observed (β=1). No degradation with time has been observed in the electrical characteristics of the chemically treated HBTs. This absence of degradation is attributed to the impermeability to oxygen of the As2S3 glass which coats the perimeter of the HBT after chemical treatment.

AlGaAs/GaAs HBTs fabricated by a self-alignment technology using polyimide for electrode separation

A self-aligned HBT (heterojunction bipolar transistor) technology using polymide for insulating the emitter contact from the base contact is described. A 1- mu m emitter-width HBT with maximum oscillation frequency of 86 GHz was successfully fabricated. This processing was also applied to fabricate frequency-divider ICs. An operating frequency of 18 GHz was obtained with good reproducibility.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The design, fabrication, and characterization of a novel electrode structure self-aligned HBT with a cutoff frequency of 45 GHz

This paper establishes a systematic approach for the design, fabrication, and modeling of a newly proposed self, aligned Al-GaAs/GaAs heterojunction bipolar transistor (HBT) employing a two-dimensional heterostructure device simulator and a heterojunction bi-polar transistor circuit simulator. The developed HBT has an abrupt emitter-base heterojunction, and applies a novel structure in which a single base electrode is placed between two emitter electrodes. A fabricated 3 × 8 µm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> two-emitter HBT exhibits a measured current gain cutoff frequency f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> = 45 GHz and a maximum oscillation frequency f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</inf> = 18.5 GHz. Results of frequency divider circuit Simulation indicate that the developed HBT would be 1.4 times faster than a conventional HBT in which one emitter electrode is located between two base electrodes.

Novel process for emitter-base-collector self-aligned heterojunction bipolar transistor using a pattern-inversion method

A process for base-emitter-collector self-aligned HBTs using a pattern-inversion method is presented. A fabricated HBT has an emitter with a size of 1.5 × 10μm2 realised by employing a dry-etching method. Typical current gain for the fabricated HBT is 26.

Emitter—Base—Collector self-aligned heterojunction bipolar transistors using wet etching process

The first emitter-base-collector (EBC) self-aligned (SA) heterojunction bipolar transistors (HBT's) using wet etching process are described. This self-alignment fabrication technique is extremely simple but can get excellent high-frequency performance. An HBT with a 4-µm-wide emitter mesa showed 18 GHz of F t and 13 GHz of F_{\max} . By optimizing this process, high-frequency operation above 40 GHz can be expected.