New self-aligned processes for III–V electronic high speed devices

Abstract

We report on two new self-aligned processes intended for microelectronic devices realization exhibiting a significant reduction of the number of elementary technological levels. These processes allow to obtain a very short self-aligned contact separation without using spacers or wet etched mesa overhangs. As an example, only three lithographic masks are used to realize a triple mesa self-aligned heterojunction bipolar transistor (HBT). A bilayer resist process is used to define the specific shape of the upper contact that is used for self-alignment. A combination of selective, isotropic, or anisotropic processes and very simple selective lift-off processes are used to define the mesa and the contacts which are also used as masks during etching. The alloying of contacts may be performed just after deposition and lift-off. These processes can reduce the production cost and increase the reliability for integration in comparison with conventional self-alignment using the selective wet etched emitter overhang in the HBT application. Furthermore, the parasitic access resistance can be reduced both by using thin mesa active layers and decreasing the contacts separation. This separation length can be determined by the aspect ratio of the bilayer resist, the characteristics, and parameters of the contact deposition equipment. At last, low induced damage inductively coupled plasma dry etch processes are partly used to reduce the dry etch damages. © 1999 American Vacuum Society.