Experimental procedure for the evaluation of GaAs-based HBT's reliability

Abstract

This work describes the implementation of an experimental procedure to evaluate the reliability of Heterojunction Bipolar Transistors (HBT) on a GaAs substrate. It is based on the separation of aging test accelerating factors applied on two test vehicles: HBT and Transmission Line Model (TLM) structures associated with emitter, base and collector layers. To identify the physical origin of the degradation mechanism, analysis techniques are used: EDX, SEM and TEM observations for which a new sample preparation method has been worked out. Three different technological fabrication processes, are investigated: AlGaAs/GaAs double-mesa HBT, GaInP/GaAs self-aligned HBT and GaInP/GaAs fully planar HBT. These investigations have revealed two major failure mechanisms: the degradation of SiN–GaAs interface correlated with the increase of emitter-to-base leakage current of HBT submitted to combined bias and temperature stresses; the detachment of Ge/Mo/W emitter ohmic contact related to the base and collector current decrease for high level injection in forward regime. A 2D simulation has lead to modify the interface electrical properties to evaluate the impact of the two degradations on HBT dc characteristics.