Enhanced etch rates of tri-level resist stacks in microwave discharges

Abstract

Thick (<or=4 mu m) tri-level resist schemes are increasingly common in processing of III-V devices such as heterojunction bipolar transistors (HBTS). Under the type of low-pressure, low-bias dry etching conditions necessary during processing of these damage-sensitive devices, conventional reactive ion etching produces impractically low etch rates. These etch rates can be substantially enhanced (sixfold) at the same pressure and bias by employing a hybrid microwave (2.45 GHz)-RF (13.56 MHz) reactor, which separates the control of the plasma density and the ion energies. Examples are given of the anisotropic etching of a tri-level resist scheme containing a PECVD SiNx transfer layer and a thick resist base layer, a typical scheme used in the processing of self-aligned HBTS.