Rms Jitter Research Articles

A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner

This work presents a low-jitter and low out-of-band noise two-core fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> digital bang-bang phase-locked loop (PLL). Two novel techniques are introduced to efficiently suppress the quantization noise (QN) of the digitally controlled oscillator (DCO) and to achieve an optimal trade between power consumption and PLL noise. The digital period averaging technique, working in background of the main system, enables the use of a low-power XOR-based quadrupler for clocking <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> modulator dithering the DCO tuning word. The true-in-phase combiner circuit implements a digitally assisted power combination of two PLL outputs, to optimally reduce the impact of the PLL noise sources. The prototype, implemented in a standard 28-nm CMOS process, has a core area of 0.47 mm2 and synthesizes frequencies from 8.5 to 10.5 GHz while dissipating 36 mW. The measured rms jitter (integrated from 1 kHz to 100 MHz and including spurs) is 72 fs for near-integer channels, with a worst case fractional spur of −59.7 dBc, while the measured out-of-band noise is −140.7 dBc/Hz at a 10-MHz offset.

A 1.6-GHz DPLL Using Feedforward Phase-Error Cancellation

A digital phase-locked loop (DPLL) using the feedforward phase-error cancellation (FPC) is presented. The phase error of this DPLL using a digitally controlled ring oscillator is quickly canceled by a digitally controlled delay line (DCDL), which improves the phase noise performance. The loop gain of this FPC DPLL is also calibrated. In addition, a dead-zone-free (DZF) bang-bang phase-frequency detector (BBPFD) is presented to enhance the resolution of the time-to-digital converter (TDC). This proposed DPLL is fabricated in a 40-nm CMOS process which occupies 0.05 mm2. The measured rms jitter integrated from 1 kHz to 100 MHz is 788 fs at 1.6 GHz. The measured reference spur is −57.84 dBc for a 50 MHz reference frequency. Its power consumption is 5 mW for a 1.1-V supply voltage.

A Calibration-Free Digital-to-Time Converter for Phase Interpolation-Based Fractional-N PLLs

In this paper, a fractional frequency division phase-locked loop based on phase interpolation is proposed and implemented using the TSMC 0.11 μm CMOS process. Compared with the conventional phase-locked loop, a digital time converter (DTC) module is added to this phase-locked loop, and the DTC module can reduce the fractional spurious by phase interpolation. The circuit and analysis method of this DTC module are given in this paper. Unlike the existing approaches, the proposed DTC is calibration-free, and the error introduced by it is only related to the DAC adopted in the DTC. In addition, the accuracy of the DTC is 8 bits. Finally, this paper verifies the proposed quantization noise reduction technique using a 0.11 μm CMOS process. The proposed FNPLL achieves the overall power consumption of 20.3 mW, the noise of −117dBc/Hz@1 MHz and −138dBc/Hz@10 MHz, and the RMS jitter of 0.860ps. The area of the proposed FDIV is 60×245μm2, and the power consumption is 1.356mW. The phase noise of the proposed FNPLL in the fractional division mode is just 2dB higher than that in the integer division mode.

16-channel photonic–electric co-designed silicon transmitter with ultra-low power consumption

A hybrid integrated 16-channel silicon transmitter based on co-designed photonic integrated circuits (PICs) and electrical chiplets is demonstrated. The driver in the 65 nm CMOS process employs the combination of a distributed architecture, two-tap feedforward equalization (FFE), and a push–pull output stage, exhibiting an estimated differential output swing of 4.0Vpp. The rms jitter of 2.0 ps is achieved at 50 Gb/s under nonreturn-to-zero on–off keying (NRZ-OOK) modulation. The PICs are fabricated on a standard silicon-on-insulator platform and consist of 16 parallel silicon dual-drive Mach–Zehnder modulators on a single chip. The chip-on-board co-packaged Si transmitter is constituted by the multichannel chiplets without any off-chip bias control, which significantly simplifies the system complexity. Experimentally, the open and clear optical eye diagrams of selected channels up to 50 Gb/s OOK with extinction ratios exceeding 3 dB are obtained without any digital signal processing. The power consumption of the Si transmitter with a high integration density featuring a throughput up to 800 Gb/s is only 5.35 pJ/bit, indicating a great potential for massively parallel terabit-scale optical interconnects for future hyperscale data centers and high-performance computing systems.

A High-Frequency and Low-Jitter DLL With Quadrature Error and Duty-Cycle Corrections Based on Asynchronous Sampling

This paper presents a quadrature error and duty-cycle correction circuit based on an asynchronous sampling technique. Sampling the multi-phased clocks provides their phase and duty-cycle information, which are then utilized to compensate for the quadrature and duty-cycle errors. The intrinsic down-conversion operation of the proposed sampling approach enhances the correction accuracy by mitigating circuit mismatch effects. The quadrature-error corrector (QEC) and duty-cycle corrector (DCC) circuits receive control signals generated from the asynchronous phase detectors and correct the clock outputs accordingly. Combined with a delay-locked loop (DLL), the proposed design is fabricated in a 40-nm CMOS process, consumes 7.2 mW, and occupies 0.023 mm. It achieves 0.837-ps RMS jitter and 1.68∘ maximum phase error from multiple chip samples.

A (0.75-1.13)mW and (2.4-5.2)ps RMS jitter Integer-N based Dual-Loop PLL for Indoor and Outdoor Positioning in 28nm FD-SOI CMOS Technology

A (0.75-1.13)mW and (2.4-5.2)ps RMS jitter Integer-N based Dual-Loop PLL for Indoor and Outdoor Positioning in 28nm FD-SOI CMOS Technology

A 0.2–7.1-Gb/s Low-Jitter Full-Rate Reference-Less CDR for Communication Signal Analyzers

For the measurement of high-speed communication signals, whether it is to check the signal’s bit error rate with a bit error rate tester or to record the signal’s eye diagram with an equivalent-time oscilloscope, a clock and data recovery (CDR) circuit is required to generate a trigger signal properly aligned to the input data signal. For the system under test where multiple communication protocols coexist, a wide operation frequency range and low jitter CDR circuit can undoubtedly improve the measurement efficiency and reduce the cost. However, obtaining broad frequency coverage and minimal recovery clock jitter simultaneously has always been a challenge in the design of CDR circuits. This paper proposes a CDR circuit combining a multi-band LC-VCO and a configurable frequency divider, which effectively expands the operating frequency range of the CDR while maintaining the low jitter of the recovered clock. A 0.2-7.1-Gb/s CDR circuits with a 1.9-ps RMS jitter of the recovered clock under a 7.1-Gb/s input PRBS signal is implemented in 65 nm CMOS. Compared with other LC-VCO based CDRs, the proposed CDR achieves better energy efficiency and lower jitter performance.

A Sub-100 fs-Jitter 8.16-GHz Ring-Oscillator-Based Power-Gating Injection-Locked Clock Multiplier With the Multiplication Factor of 68

This work presents an ultralow-jitter ring-oscillator (RO)-based injection-locked clock multiplier (ILCM). Using the power-gating (PG) injection method that can completely remove the accumulated phase error of the RO, the proposed ILCM can achieve a very wide injection bandwidth, and, thus, an ultralow-jitter, even when the multiplication factor, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${N}$ </tex-math></inline-formula> , is increased above 60. To overcome the natural limitation of the PG injection, two digitally controlled oscillators (DCOs) were used to operate in a complementary manner. Since the background multi-functional calibrator (MFC) continuously synchronizes the outputs of the two DCOs, the PG-ILCM can generate a seamless output signal by combining these two signals. The proposed injection pulsewidth controller (IPWC) decreased the required delay of the digital-to-time converter (DTC), further reducing the jitter of the output signal. A phase-rotational divide-by-4 divider (PR-DIV4) also was proposed to reduce the operating frequency and the power consumption of the MFC while maintaining the fine resolution of the output frequency. The PG-ILCM, fabricated in a 65-nm CMOS process, used the power of 14.3 mW and an area of 0.102 mm2. The rms jitter measured at 8.16 GHz ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N = 68$ </tex-math></inline-formula> ) was 97 fs.

An Attachable Fractional Divider Transforming an Integer-N PLL Into a Fractional-N PLL Achieving Only 0.35-psrms-Integrated-Jitter Degradation With SSC Capability

PLLs are utilized in SoCs for automotive industry. In the industry, the system handles with satellite signals which are weak radio waves coming from space. Therefore, the output frequency of PLLs is carefully designed to avoid EMI. Recently, Global Navigation Satellite System (GNSS) is becoming more common and available frequency bands for clocks are getting narrow. That leads, in many products, replacement integer-N PLLs with fractional-N PLLs is needed to obtain smaller output frequency steps than reference frequency. The attachable fractional divider introduced in this talk transforms an integer-N PLL into a fractional-N PLL with only 0.35 psrms of integrated RMS jitter degradation.

A Supply-Noise-Induced Jitter Canceling Adaptive Filter for LPDDR5 Mobile DRAM

This article presents a supply-noise-induced jitter (SIJ) cancellation technique based on an adaptive filter (AF) using a least mean-square (LMS) algorithm. It cancels jitter along with the clock distribution network (CDN) and the transmit paths, which include serializers and pre-drivers. The proposed technique includes a second-order AF to maximize jitter cancellation in the clock path, which has a nonlinear supply-to-jitter characteristic. Implemented in 28-nm CMOS, the proposed SIJ cancellation scheme reduces the rms jitter of the output clock from 27.84 to 4.28 ps and improves the data eye-opening from 22.43 to 104.73 ps when operating at 6.4 Gb/s with a 60-mVPP, 1-MHz supply noise.

A Fractional-N CP-PLL with fast two-point modulation calibration using duty-cycle and polarity tracking technique in 110-nm CMOS

This article proposes a fractional-N charge pump phase-locked loop (CP-PLL) with fast two-point modulation calibration using Duty-Cycle and Polarity Tracking technique. The proposed calibration method can perform delay and gain calibration within 15 μs, respectively. A DTC-assisted Polarity Detector is used to track and countervail the propagation delay of two modulation paths. A TDC-based Duty-Cycle Detector is used to monitor and compensate the two paths gain mismatch. By comparing the code with the threshold set in the look-up table (LUT), a quick calibration can be achieved. To maintain high out-band phase noise performance and stronger robustness, a Class-C oscillator using Capacitance Desensitization technique and Cross-Bias technique is adopted in the design. The proposed CP-PLL is implemented in a standard 110-nm CMOS technology, occupying 2.7 mm2 silicon area. The post-simulation results show the proposed calibration method can calibrate the delay/gain mismatch within 30 μs. Fast calibration mode supports calibration time within 62.5 ns. The phase noise performance is −91-dBc/Hz@100 kHz, −119-dBc/Hz@1 MHz. The entire CP-PLL dissipates 20.9-mW and achieves an RMS jitter of 6.2 ps, corresponding to a figure of merit (FOM) of −211-dB.

A Low-Jitter Ring-DCO-Based Fractional-N Digital PLL With a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector

This work presents a fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> ring-oscillator (RO)-based digital phase-locked loop (DPLL). To achieve ultralow jitter, the proposed RO-DPLL used a technique to reduce the dominant source of in-band noise, i.e., the thermal noise of the digital-to-time converters (DTCs). A key building block of this technique is the quadruple-timing-margin phase selector (QTM-PS) that dynamically selects the proper phase among the eight phases of the RO, effectively reducing the required dynamic range of the DTCs and, thus, suppressing the thermal noise significantly. Based on the reduced in-band noise, the dual-edge generator (DEG) doubles the bandwidth of the DPLL, further suppressing the jitter of the RO. The integrated background calibrator (IBC) that can perform multiple least mean squares (LMS)-based calibrations was used to guarantee the stable operation and performance of both the QTM-PS and the DEG. The proposed RO-DPLL was fabricated in 65-nm CMOS, and it used 0.139-mm2 silicon area and 15.67-mW power. At a fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> frequency near 5.2 GHz, the rms jitter and the figure of merit (FoM) of the output signal were 188 fs and–243 dB, respectively.

A 6-to-7.5-GHz 54-fsrms Jitter Type-II Reference-Sampling PLL Featuring a Gain-Boosting Phase Detector for In-Band Phase-Noise Reduction

This paper presents a type-II reference-sampling (RS) phase-locked loop (PLL) exploiting a novel gain-boosting reference-sampling phase detector (RSPD) to reduce the in-band phase noise and RMS jitter. The proposed gain-boosting RSPD converts the phase error to the voltage error and utilizes a passive switched-capacitor voltage multiplier to amplify the sampled voltage error, which effectively increases the gain of the RSPD. The boosted RSPD gain helps suppress the phase noise contributed from the gm cell. To prevent the transistors in the gain-boosting RSPD and gm cell from breakdown, the gain-boosting function is only activated during the locked state when the phase and voltage errors are small. The switching between the gain-boosting and normal modes is realized automatically by monitoring the sampled voltage and comparing it with a pre-defined threshold window. Fabricated in 65-nm CMOS, the type-II RS-PLL measures an RMS jitter of 54 fs at 6.75 GHz and consumes 7.1 mW, corresponding to a jitter figure-of-merit (FoMjitter) of −256.8 dB. The measured reference spur is −62.6 dBc, and the active area is 0.25 mm2.

Supply-Noise-Desensitized Techniques for Low Jitter RO-Based PLL Achieving ≤1.6 ps RMS Jitter Within Full-Spectrum Supply Interference

This paper presents a supply-noise-robust PLL that achieves low-jitter performance within full-spectrum supply interference. A digital-regulated supply noise cancellation (DSNC) scheme suppresses the large amplitude supply noise within an adequate range for a supply-noise-insensitive (SNI) VCO. It ensures that the low pushing factor SNI-VCO only induces a decent amount of phase noise falling within the effective correction range of the phase noise cancellation (PNC). A sample-and-isolate-based (S/I)-PNC cascaded at the VCO output enables a wider correction range for a fine supply noise and phase noise suppression. Fabricated in 28-nm CMOS with an area of 0.088 mm2, the proposed PLL consumes 6.65 mW from a 1 V supply at 4 GHz output. With 20 mVpp supply interference, the prototype obtains a maximum >37 dB output spur reduction at 5 MHz and maintains ≤1.6 ps RMS jitter in the worst case. The suppression performance degrades less than 10% within −20 °C to 80 °C operation temperature.

A Cost-Effective and Compact All-Digital Dual-Loop Jitter Attenuator for Built-Off-Test Applications

A compact and low-power all-digital CMOS dual-loop jitter attenuator (DJA) for low-cost built-off-test (BOT) applications such as parallel multi-DUT testing is presented. The proposed DJA adopts a new digital phase interpolator (PI)-based clock recovery (CR) loop with an adaptive decimation filter (ADF) function to remove the jitter and phase noise of the input clock, and generate a phase-aligned clean output clock. In addition, by adopting an all-digital multi-phase multiplying delay-locked loop (MDLL), eight low-jitter evenly spaced reference clocks that are required for the PI are generated. In the proposed DJA, both the MDLL and PI-based CR are first-order systems, and so this DJA has the advantage of high system stability. In addition, the proposed DJA has the benefit of a wide operating frequency range, unlike general PLL-based jitter attenuators that have a narrow frequency range and a jitter peaking problem. Implemented in a 40 nm 0.9 V CMOS process, the proposed DJA generates cleaned programmable output clock frequencies from 2.4 to 4.7 GHz. Furthermore, it achieves a peak-to-peak and RMS jitter attenuation of –25.6 dB and –32.6 dB, respectively, at 2.4 GHz. In addition, it occupies an active area of only 0.0257 mm2 and consumes a power of 7.41 mW at 2.4 GHz.

A Fractional-N Synthesizable PLL Using DTC-Based Multistage Injection With Dithering-Assisted Local Skew Calibration

A standard-cell-based fractional-N synthesizable phase-locked loop (PLL) [or multiplying-delay-locked loop (MDLL)] is proposed, where the multiple phases of the three-stage ring digitally controlled oscillator (DCO) are utilized for injection. The required digital-to-time converter (DTC) range is reduced to one third of the DCO’s period, resulting in higher linearity, less jitter, lower power consumption, and smaller area. The issue of the mismatches among DCO’s stages is solved by the proposed dithering-assisted local skew calibration, which removes the skews in the injection path and smears out the periodic pattern at the PLL side to reduce spurs. Most of the dithering noise is suppressed by the injection locking and the phase tracking loop. Measured at 1.0095-GHz output frequency with 24-MHz reference frequency, with the proposed solution, the integrated root-mean-square (rms) jitter can be reduced from 6.40 to 2.55 ps, and the power consumption is 3.36 mW. This translates to −226.6-dB figure of merit (FoM) and −232.8-dB FoM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ref</sub> . The measured fundamental fractional spurs range from −56 to −45 dBc.

A 0.8–3.2 GHz PLL with wide frequency division ratio range

An improved phase-locked loop (PLL) with a wide frequency division ratio range is presented. A digital to analog converter (DAC) is used to separate the proportional path and integral path, thus the dynamic performance of PLL can be flexibly adjusted by DAC and the current-controlled oscillator (CCO). As the resistor in the second-order PLL is replaced by an equivalent circuit, the implemented PLL is insensitive to the process, voltage, and temperature (PVT) variation. Decoupling the relationship between loop bandwidth ωb and division ratio N improves the overall performance over a wide dynamic output frequency range. The PLL was implemented in TSMC 22 nm CMOS process and the chip occupies an area of 0.04 mm2. The measured output frequency is ranged from 0.8 GHz to 3.6 GHz. The phase noise is −107.3dBc@1 MHz and the integrated RMS jitters at 1.92 GHz is 3.36ps. The total power consumption at 1.92 GHz is 4.2 mW.

A Programmable Multiple Frequencies Clock Generator With Process and Temperature Compensation Circuit for System on Chip Design

This article presents a programmable multiple frequencies clock generator with a process and temperature compensation circuit design. The proposed clock generator can achieve a stable and wide frequency range output for a single input frequency by using digital control codes as well as process and temperature compensation mechanisms. In our approach, the first step is to adjust the duty-cycle of the input clock by using a digitally controlled pulsewidth modulator (DCPWM) to generate an output clock signal with a duty-cycle of 20% to 80%. Second, the various duty-cycle clock outputs of the DCPWM are integrated by the duty-cycle-to-voltage converter to generate analog voltage signals to control the succeeding voltage-controlled ring oscillator (VCO). Through the use of various control voltages, different VCO output frequencies are generated. Finally, by using the process and temperature compensation circuit, the proposed clock generator can provide a stable and wide frequency range. The proposed chip is fabricated in a 180-nm CMOS process and has an output frequency range of 35–138 MHz at a supply voltage of 0.9 V. At 120 MHz, the power dissipation and rms jitter are 224.3 μW and 7.84 ps, respectively. The active area of the chip is 0.62 mm × 0.76 mm.

A 23.4 mW −72-dBc Reference Spur 40 GHz CMOS PLL Featuring a Spur-Compensation Phase Detector

This letter introduces a novel phase detector (PD) for suppressing the reference spur in a 40 GHz integer- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> phase-locked loop (PLL). Coined as a spur-compensation phase detector (SCPD), the proposed SCPD duplicates itself to an auxiliary path for an edge-combined phase alignment, such that the spurs generated by the two paths mutually compensate for each other, achieving a net effect of spur canceling. Implemented in a 40-nm CMOS technology, the proposed PLL shows less than −71.4-dBc reference spur, −98- and −117-dBc/Hz phase noise at 1- and 10-MHz offset, respectively, and a minimum rms jitter of 114 fs (10 k–100 MHz). It consumes 23.4-mW power from a 1.1-V power supply, leading to a figure of merit (FoM) of −245 dB.

A low noise 5.12 GHz PLL ASIC in 55 nm for NICA multi purpose detector project

This paper presents the design and the test results of a low noise PLL ASIC for the optical data transmission system in NICA MPD project. In the proposed PLL, a novel charge pump circuit uses two feedback operational amplifiers to obtain low leakage current and reduce dynamic mismatch. A LC-VCO circuit combines the two-step capacitor tuning structure and the novel capacitor array unit to obtain a reasonable frequency range and an optimized Q factor performance. The PLL ASIC has been fabricated in a 55 nm CMOS process. The test results show that the PLL ASIC outputs the 5.12 GHz clock with a phase noise of −108 dBc/Hz at 1 MHz offset and a rms jitter of 880 fs. The PLL core consumes 22.2 mW from a 1.2 V power supply.