A Fractional-N Synthesizable PLL Using DTC-Based Multistage Injection With Dithering-Assisted Local Skew Calibration

Abstract

A standard-cell-based fractional-N synthesizable phase-locked loop (PLL) [or multiplying-delay-locked loop (MDLL)] is proposed, where the multiple phases of the three-stage ring digitally controlled oscillator (DCO) are utilized for injection. The required digital-to-time converter (DTC) range is reduced to one third of the DCO’s period, resulting in higher linearity, less jitter, lower power consumption, and smaller area. The issue of the mismatches among DCO’s stages is solved by the proposed dithering-assisted local skew calibration, which removes the skews in the injection path and smears out the periodic pattern at the PLL side to reduce spurs. Most of the dithering noise is suppressed by the injection locking and the phase tracking loop. Measured at 1.0095-GHz output frequency with 24-MHz reference frequency, with the proposed solution, the integrated root-mean-square (rms) jitter can be reduced from 6.40 to 2.55 ps, and the power consumption is 3.36 mW. This translates to −226.6-dB figure of merit (FoM) and −232.8-dB FoM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ref</sub> . The measured fundamental fractional spurs range from −56 to −45 dBc.