25.5 A Self-Calibrated 1.2-to-3.8GHz 0.0052mm2 Synthesized Fractional-N MDLL Using a 2b Time-Period Comparator in 22nm FinFET CMOS

Abstract

Increasing speed and complexity of modern SoCs demand low-jitter clock generators, which conventionally use LC resonators. But, low power operation at sub-6GHz frequencies requires large L, increasing the form factor. Digital multiplying delay-locked loops (MDLL) [1], [2] or injection-locked phased-locked loops (IL-PLL) [3] based on ring oscillators (ROSCs) are preferred due to their smaller form factor and superior jitter performance than that of basic PLLs. Using a ROSC as a digitally controlled oscillator (DCO) enables a fully synthesizable design solution, which has the benefit of easy portability to scaled technologies while greatly reducing the design effort and complexity associated with manual placements of layout cells and design rule checks [3]–[6]. However, a synthesizable design needs to be insensitive to layout parasitics and mismatches, which makes the design of an MDLL or IL-PLL challenging. The performance is much worse in fractional-N architectures due to the stringent gain and linearity requirement of the digital-to-time converter (DTC) [2], [3] or time-to-digital converter (TDC) [4], [6]. [3] uses digital standard cells to implement blocks with analog functionality. That makes the design synthesizable but sensitive to process-voltage-temperature (PVT) variations, requiring careful device sizing. A dual-reference TDC in [4] reduces the PVT sensitivity but uses same TDC for each DCO phase, adding significant power and area overhead. This paper presents a synthesizable fractional-N MDLL using a 2b time-period comparator (TPC). The TPC comprises a tunable reference delay $(\uparrow_{\mathrm{p}})$ and a 2b phase detector (PD). It adjusts the DCO period $(\mathrm{T}_{\mathrm{DCD}})$ and $\mathrm{T}_{\mathrm{P}}$ using two independent feedback loops operating simultaneously. A TPC based bang-bang PD was implemented in [1], but 1b output to control both $\mathrm{T}_{\mathrm{DCD}}$ and $\mathrm{T}_{\mathrm{P}}$ requires an initial calibration to reduce the PLL lock time and avoid lock failure as $\mathrm{T}_{\mathrm{DCD}}$ continuously updates in alternate cycles. In this work, the 2b output in the proposed TPC provides automatic tuning of $\mathrm{T}_{\mathrm{DCO}}$ and $\mathrm{T}_{\mathrm{P}}$ without additional calibration. Faster locking can be achieved over a wide range of resolutions, hence making it synthesizable. Furthermore, the MDLL uses a replica of the DCO to implement the DTC for fractional-N generation, which self-calibrates its gain to suppress the fractional spurs.