Abstract
This article presents a supply-noise-induced jitter (SIJ) cancellation technique based on an adaptive filter (AF) using a least mean-square (LMS) algorithm. It cancels jitter along with the clock distribution network (CDN) and the transmit paths, which include serializers and pre-drivers. The proposed technique includes a second-order AF to maximize jitter cancellation in the clock path, which has a nonlinear supply-to-jitter characteristic. Implemented in 28-nm CMOS, the proposed SIJ cancellation scheme reduces the rms jitter of the output clock from 27.84 to 4.28 ps and improves the data eye-opening from 22.43 to 104.73 ps when operating at 6.4 Gb/s with a 60-mVPP, 1-MHz supply noise.
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