A Jitter Cancellation Circuit for High Speed I/O Interfaces

Abstract

A novel Jitter Cancellation Circuit (JCC) that reduces deterministic clock jitter induced by supply noise is designed. High Speed IO interface circuits require low deterministic clock jitter in order to meet the timing budget. Supply noise is a primary contributor of deterministic jitter. As data rates are scaling to higher frequencies, the acceptable jitter due to supply noise is decreasing. For a CMOS Inverter, the clock delay decreases when the instantaneous supply voltage increases leading to positive clock jitter. This jitter compensation circuit introduces negative jitter on the clock distribution path which means an instantaneous increase in supply voltage leads to an increase in delay so that the positive jitter can be cancelled out. The JCC provides programmable controls to tune the amount of jitter cancellation and also provides Process, Voltage and Temperature (PVT) tracking jitter cancellation mode so that there is higher cancellation in process corners (Slow Silicon, lower supply voltage) that are more susceptible to noise. With the jitter cancellation circuit, there is 5× clock jitter reduction with only 0.15% power head. This is implemented on latest deep-submicron digital process.