A 23.4 mW −72-dBc Reference Spur 40 GHz CMOS PLL Featuring a Spur-Compensation Phase Detector

Abstract

This letter introduces a novel phase detector (PD) for suppressing the reference spur in a 40 GHz integer- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> phase-locked loop (PLL). Coined as a spur-compensation phase detector (SCPD), the proposed SCPD duplicates itself to an auxiliary path for an edge-combined phase alignment, such that the spurs generated by the two paths mutually compensate for each other, achieving a net effect of spur canceling. Implemented in a 40-nm CMOS technology, the proposed PLL shows less than −71.4-dBc reference spur, −98- and −117-dBc/Hz phase noise at 1- and 10-MHz offset, respectively, and a minimum rms jitter of 114 fs (10 k–100 MHz). It consumes 23.4-mW power from a 1.1-V power supply, leading to a figure of merit (FoM) of −245 dB.