一個0.02mm2之鎖相迴路並採用次取樣與突波降低技術實現於90nm CMOS製程

Abstract

The thesis implements a small area sub-sampling phase-locked loop(PLL) with spur reduction technique. Nowadays, CPUs adopt a number of PLLs for individual core in order to save the power consumption by dynamically adjusting the operation frequency. Along with the progress in process, the cost per unit area keeps increasing. Therefore, the area of PLL needs to be shrunk with the same performance.In the conventional PLL, the loop filter is composed of passive capacitor which occupies the most parts of chip area. As a result, the area of PLL can be saved by replacing the passive capacitor which stores or releases the charges with a current-controlled oscillator and a dummy oscillator which store the phase information. To reduce the output phase noise, the thesis adopts sub-sampling technique. As the output frequency is locked and the phase difference between reference and divider output is less than 180°, the frequency-locked loop is turned off and the sub-sampling phase detector with higher gain dedicates on phase locking. Meanwhile, the divider path is turned off so as to avoid the divider from contributing phase noise to system. However, the sub-sampling technique has three side effects and reference spur is raised up by those disadvantages. Hence, this thesis adopts spur reduction technique to alleviate those disadvantages from sub-sampling technique.This chip is fabricated in TSMC 90nm CMOS technology with an active area of 0.02mm^2 and 2GHz operation frequency. The reference spur is -49.42 dBc and phase noise is -80.32 dBc/Hz at 1MHz offset from carrier frequency under 1.2V power supply with 8.68mW power dissipation.