Supply-Noise-Desensitized Techniques for Low Jitter RO-Based PLL Achieving ≤1.6 ps RMS Jitter Within Full-Spectrum Supply Interference

Abstract

This paper presents a supply-noise-robust PLL that achieves low-jitter performance within full-spectrum supply interference. A digital-regulated supply noise cancellation (DSNC) scheme suppresses the large amplitude supply noise within an adequate range for a supply-noise-insensitive (SNI) VCO. It ensures that the low pushing factor SNI-VCO only induces a decent amount of phase noise falling within the effective correction range of the phase noise cancellation (PNC). A sample-and-isolate-based (S/I)-PNC cascaded at the VCO output enables a wider correction range for a fine supply noise and phase noise suppression. Fabricated in 28-nm CMOS with an area of 0.088 mm2, the proposed PLL consumes 6.65 mW from a 1 V supply at 4 GHz output. With 20 mVpp supply interference, the prototype obtains a maximum >37 dB output spur reduction at 5 MHz and maintains ≤1.6 ps RMS jitter in the worst case. The suppression performance degrades less than 10% within −20 °C to 80 °C operation temperature.