Replacement Metal Gate Research Articles

(Invited) Selective Etches for Gate-All-Around (GAA) Device Integration: Opportunities and Challenges

This paper addresses the opportunities and challenges of wet and dry selective etches in the integration of gate-all-around (GAA) field-effect transistor (FET), which is emerging as a promising solution to replace FinFET for the advanced logic devices. For the GAA device fabrication, a quintessential challenge is a controlled isotropic etching of dielectrics, semiconductors, and metals with high selectivity to the exposed materials. In this paper, the significance of the unit process modules in the GAA device integration: shallow trench isolation (STI), inner spacer formation, replacement metal gate (RMG) and self-aligned interconnect in the middle-of-line (MOL) and the back-end-of-line (BEOL), will be discussed.

Modeling of HCD Kinetics for Full ${V}_{{G}}$ /${V}_{{D}}$ Span in the Presence of NBTI, Electron Trapping, and Self Heating in RMG SiGe p-FinFETs

A SPICE compatible compact modeling framework is proposed for the time kinetics of threshold voltage shift ( $\Delta {V}_{T}$ ) in FinFETs subjected to hot carrier degradation (HCD) stress. The model is valid for the entire drain ( ${V}_{D}$ ) and gate ( ${V}_{G}$ ) voltage space and calculates the generation of interface traps for pure HCD ( $\Delta {V}_{\text {IT-HC}}$ ) and for negative bias temperature instability (NBTI) ( $\Delta {V}_{\text {IT-BT}}$ ), hole trapping ( $\Delta {V}_{\text {HT}}$ ), and electron trapping ( $\Delta {V}_{\text {ET}}$ ) as necessary, and considers the self-heating effect (SHE). The model is validated by using ultrafast (10- $\mu \text{s}$ delay) measured data from replacement metal gate (RMG) silicon germanium (SiGe) p-FinFETs having a different fin length (FL) and different nitrogen (N%) in the gate insulator stack. A calibrated TCAD framework is used to verify the impact of pure NBTI for varying ${V}_{G}$ and ${V}_{D}$ stress in the presence of SHE but no HCD.

3-D Sequential Stacked Planar Devices Featuring Low-Temperature Replacement Metal Gate Junctionless Top Devices With Improved Reliability

3-D sequential integration requires top MOSFETs processed at a low thermal budget, which can impair the device reliability. In this paper, top junctionless (JL) devices are fabricated with a maximum processing temperature of 525 °C. The devices feature high k/metal replacement gate and low-temperature Si:P and SiGe:B 60% raised source and drain for nMOS and pMOS fabrication, respectively. Device matching, analog, and RF performance of the top tier devices are in-line with the state-of-the-art Si technology processed at high temperature (>1000 °C). JL devices operate at reduced electric field and can meet in specification reliability (10-year reliable operation at ${V}_{\textsf {G}}= {V}_{\textsf {th}}+ 0.6$ V, 125 °C), even without the use of “reliability” anneal. The top Si layer is transferred on CMOS planar bulk wafers with W metal-1 interconnects, using a SiCN to SiCN direct wafer bonding. Comparison with silicon-on-insulator devices fabricated with the same low-temperature flow shows no impact on device electrical performance from the Si layer transfer.

Understanding PBTI in Replacement Metal Gate Ge n-Channel FETs With Ultrathin Al2O3 and GeO<italic>x</italic> ILs Using Ultrafast Charge Trap–Detrap Techniques

We report positive bias temperature instability data in replacement metal gate Ge n-channel metal–oxide–semiconductor field-effect transistors with an in-situ gate stack employing an ultrathin (5 A), stable Al2O3 interlayer (IL) using ultrafast (~microseconds) characterization techniques that ensure recovery artifact-free measurements. Comparison with state-of-the-art GeO x IL is also reported besides establishing correlations between band-edge interface trap density ( ${D}_{\text {it}}$ ), mobility ( $\mu$ ), and threshold voltage ( ${V}_{T}$ ) instability. Ultrafast measure-stress-measure (UF-MSM), ultrafast measure-stress-detrap-measure (UF-MSDM), stress-induced-leakage-current (SILC), direct-current current–voltage (DCIV), split capacitance–voltage ( ${C}$ – ${V}$ ), and low-temperature full conductance techniques along with a compact model demonstrate that: 1) trap generation occurs at IL/high- ${k}$ interface during stress; 2) an increase in $\mu$ with reduction in ${D}_{\text {it}}$ does not guarantee better reliability, i.e., ${V}_{T}$ shift and $\mu$ are uncorrelated due to their dependence on separate regions of the gate stack; 3) contributions to total ${V}_{\text {T}}$ degradation from trapping and generated traps are mutually exclusive; 4) UF-MSDM is a powerful tool to estimate trap generation; and 5) ${V}_{T}$ degradation is directly proportional to high- ${k}$ thickness, varies inversely with IL thickness, and reduces with annealing.

RMG Patterning by Digital Wet Etching of Polycrystalline Metal Films

A self-limiting wet etching of metal thin films has been developed for the replacement metal gate patterning in advanced logic devices, which will have aggressively scaled gate length and fin pitches. A uniform and highly selective wet etching of polycrystalline TiN films is demonstrated by a diffusion-limiting oxide growth on the metal surfaces as well as a subsequent highly selective oxide removal.

Band-Edge Work Function Obtained by Plasma Doping TiN Metal Gate for nMOS Device Application

This paper proposed, for the first time, that the band-edge effective work functions (EWFs) are achieved by employing PH3 plasma doping (PLAD) TiN metal gate for nMOS device application under replacement metal gate and high dielectric constant (k) dielectric/metal gate last nMOS device. The effects of PLAD energy, dose, gas mixture, and postdoping cleaning procedure on the EWF, EOT, and properties of TiN/HfO2/ILSiO2 gate-stack are investigated; the corresponding possible mechanisms are discussed. Suitable low threshold voltages of nMOSFETs are obtained, while shrinking the EOT. It reduces the corner effect on trench gate doping uniformity, which is induced by shadowing effect in the beam-line implantation technology, to a minimum. It has the potential for the further aggressively scaled 3-D CMOS device and beyond application.

Extraction of Drain Current Thermal Noise in a 28 nm High-<inline-formula> <tex-math notation="LaTeX">${k}$ </tex-math> </inline-formula>/Metal Gate RF CMOS Technology

This paper investigates RF noise in a 28-nm replacement metal gate RF CMOS technology. The gate resistance is shown to be limited by interfacial resistance in metal gate stack. Intrinsic noise factor $\gamma _{\mathrm{ gd0}}^{\mathrm{ int}} ={S}_{\mathrm{ id}}^{\mathrm{ int}}/\text{4kTg}_{\mathrm{ d0}}$ and shot noise suppression factor ${k}_{s}^{\mathrm{ int}} = {S}_{\mathrm{ id}}^{\mathrm{ int}}/\text{2qI}_{\mathrm{ DS}}$ are extracted. $\text{g}_{\mathrm{ d0}}$ from S-parameters is shown to be more accurate than from dc ${I}$ – ${V}$ . $\gamma _{\mathrm{ gd0}}^{\mathrm{ int}}$ remains less than 2, despite a large increase from 90-nm gate length, as well as a much stronger increase with ${V}_{\mathrm{ DS}}$ . ${k}_{s}^{\mathrm{ int}}$ shows a decrease on ${V}_{\mathrm{ GS}}$ and a weak increase on ${V}_{\mathrm{ DS}}$ . Of all four noise parameters, noise resistance plays the most significant role in intrinsic drain current noise extraction. Extrinsic and intrinsic noise resistance can be modeled by simple expressions.

Novel GAA Si Nanowire p-MOSFETs With Excellent Short-Channel Effect Immunity via an Advanced Forming Process

In this letter, Gate-All-Around (GAA) nanowire (NW) p-MOSFETs with new approaches to fabricate totally isolated channels in replacement metal gate (RMG) are reported for the first time. Few reformed fin forming processes based on conventional high- k /metal gate FinFET flow are implemented to fabricate the GAA devices. Two profiles of NW channels, such as circular and inverted droplet, were fabricated by H2 baking and oxidation methods in the RMG process. The proposed methods would increase the process thermal budget and improve film quality for the NW channels. Providing both structural and process advantages, the optimized devices with $L_{g} = 16$ nm demonstrate superb short-channel effect (SCE) immunity characteristics, with SS = 61.86$ mV/dec and DIBL = 6.5 mV/V for the inverted droplet NW device; these results are very close to the ideal limits of MOSFETs. The results also indicate that the inverted droplet NW devices have a slightly better SCE control than the circular NWs of similar geometric size.

New charge pumping current model assuming exponential tails in the trap energy distribution

In this letter, a new charge pumping current expression is derived by assuming an exponential distribution of traps. This modified expression leads to a different method of extracting the trap emission time constant. This approach is applied on FinFET transistors with high- $\kappa $ replacement metal gate stack to evaluate experimentally the impact of this correction compared to the original expressions from the previous works. It is found that the difference with customary methods is small, although it may potentially distort the temperature dependence of the trap emission rate.

Material lattice orientation effect of local Si1-xGex stressors on the width dependence of high-k metal gate PMOSFETs

The novel material selection and fabrication became a major concern due to scaling limitations when the technology node was below 20 nm. Complex gate-last process step for high-k metal gate (HKMG) device was proposed to enhance device mobility gain through the proper assistance of boosting channel stress. However, the impact of anisotropic material behavior regarding SiGe and silicon device is rarely estimated. Thus, the foregoing mechanical responses combined with concerned device layout during gate etch, replacement metal gate must be investigated. In this study, a process-oriented simulation methodology was presented to investigate this critical issue by a vehicle of 20 nm short-channel HKMG p-type MOSFET with embedded SiGe alloy stressor. Results indicated that the poly gate etch process significantly improved the longitudinal channel stress (Sxx) of this device channel. Process-induced Sxx values of −306.94 and −1325.48 MPa were obtained when the gate-first and gate-last processes were estimated, and 100 nm gate width was achieved, respectively. Given the increase in gate widths from 100 nm to 4000 nm, the maximum carrier mobility of 116.57% and 111.01% were obtained when isotropic and anisotropic material properties were adopted.

Demonstration of 3-D SRAM Cell by 3-D Monolithic Integration of InGaAs n-FinFETs on FDSOI CMOS With Interlayer Contacts

In this paper, we demonstrate, for the first time, 3-D Monolithic integration of short-channel replacement metal gate InGaAs n-FinFETs on fully-depleted silicon-on-insulator CMOS, with TiN/W interlayer contacts. Top layer InGaAs nFETs feature raised source–drain and bottom layer CMOS has Si raised source–drain for nFETs, SiGe raised source–drain for pFETS, implants, silicide, and TiN/W plug contacts. Scaled gate length ( ${\text L}_{\text g}$ ) of 15 nm is achieved on bottom layer Si n- and pFETs, while the top layer InGaAs n-FinFETs are scaled to ${\text L}_{\text g}$ of 25 nm. A densely integrated 3-D 6T-static random access memory circuit with planar InGaAs nFETs stacked on Si pFETs is demonstrated by taking advantage of the interlayer contacts. This yields significant area reduction when compared with 2-D layouts.

The Impact of Dummy Gate Processing on Si-Cap-Free SiGe Passivation: A Physical Characterization Study on Strained SiGe 25% and 45%

High mobility channel materials like SiGe, Ge and IIIV receive lots of interest in order to enable the continuation of Moore’s path during the upcoming technology nodes. Recently Si-cap-free SiGe passivation with the number of interface states (NIT) down to 2 1011 cm-2 have been demonstrated. [1-3] A clear correlation was established between Ge-content in the SiGe-oxide and NIT. Unfortunately no process information has been provided on how the Ge-oxide-free interlayers were obtained. In a separate study the impact of HF, HCl and SC1 cleaning solution on the SiGe surface and oxide composition was reported. [4] A comparison of SiGe Gate-All-Around (GAA) and FinFET devices using a Si-cap-free SiGe 25% passivation scheme in a replacement metal gate (RMG) integration indicate the device performance is improved by a TMAH (aq) treatment prior to SiGe interlayer formation and high-k deposition. [5] Here the formation of a SiGe wet chemical oxide will be presented. The impact of dummy gate processing on the interlayer composition is reported. Also the impact of a TMAH (aq) treatment prior to chemical oxide formation has been analyzed and will be reported. Blanket strained SiGe 25% and 45% were grown by epitaxy. The SiGe-substrate and -oxide composition were measured by angle-resolved XPS using the Si2p and Ge3d peaks. The Ge3d peak is fitted with three different compounds: elemental Ge, GeO2 and Ge-suboxide. The angle dependence lets us estimate the distribution of the different components with respect to the sample top surface. An concentration increase with increasing angle (relative to the surface normal) indicates the compound is located closer to the sample surface. And reversely a concentration increase with increasing angle indicates the compound is located deeper into the sample. A native oxide was grown on SiGe 25 and 45% by exposing the wafers to the cleanroom air for approx. 1 week. The native oxide was found to be stoichiometric or nearly stoichiometric with a uniform Ge content throughout the oxide for SiGe 25 and 45% respectively. A wet chemical oxide was grown using an ‘imec clean’ [6] having a final O3/HCl (aq) rinse. The wet chemical oxide is Ge-poor compared to the SiGe substrate. No or only a small variation in Ge content of the SiGe-oxide is seen with ARXPS. However the fraction Ge-suboxide decreases with increasing angle, indicating the Ge-suboxide are located deeper within the sample, so closer to the SiGe-oxide/SiGe-substrate interface. The Ge-content of the SiGe-substrate after wet chemical oxidation shows a weak incident-angle-dependence, indicative a limited Ge enrichment of the SiGe substrate towards the SiGe-oxide/-substrate interface. The low Ge content of the SiGe-oxide is attributed to the water solubility of GeO2. The increase in Ge-content towards the SiGe-oxide/-substrate can be (at least partially) attributed to the poor water solubility of Ge-suboxide. The small increase in Ge content of the SiGe substrate can be attributed to the thermodynamically preferred oxidation of Si over Ge. The combined impact of dummy gate deposition, spike anneal and dummy gate removal prior to SiGe interlayer formation was investigated by AR-XPS and SIMS. The temperature used during spike anneal was found to have a significant impact on the Ge-content of the SiGe-oxide formed during an O3-last imec clean. The results will be reported in detail at the conference. The impact of TMAH (aq) on the chemical oxide composition and surface roughness will also be reported. TMAH (aq) was found to improve SiGe device performance. [5] Also the interaction with the subsequent HfO2 deposition will be reported. In summary SiGe is found to behave as a non-linear combination of Si and Ge. In HF-free aqueous solutions, the SiGe oxide composition is a combination of (1) thermodynamically preferred oxidation of Si versus Ge; (2) poor water-solubility of SiO2 and/or its low solubilization rate; and (3) fast dissolution of GeO2 but slow dissolution of Ge-suboxides. [1] CH Lee et al. VLSI 2016. [2] S. Siddiqui et al. presented MRS Spring Meeting 2016. [3] CH Lee et al. IEDM 2016. [4] S.L. Heslop et al. ECS Trans 69 (2015) 287. [5] H. Mertens et al VLSI 2015. [6] M. Meuris et al. Solid State Phenom, July 1995, p. 109. Figure 1

(Invited) Challenges on Surface Conditioning in 3D Device Architectures: Triple-Gate FinFETs, Gate-All-Around Lateral and Vertical Nanowire FETs

Over the past decades, aggressive and continuous transistor scaling according to Moore’s law has enabled new system features thanks to ever increasing device performance and density, reduced cost and power consumption. To keep the industry’s growth rate, triple-gate finFETs were recently implemented into manufacturing at the 22nm technology node [1]. These devices continue to be the subject of many innovations but face increasing scaling challenges for advanced (sub-)5nm nodes, with gate-all-around (GAA) nanowire (NW) FETs representing their ultimate scaling limit and being one of the most promising candidates to further support the CMOS roadmap (Fig. 1) [2-5]. In this work, we address some of the challenges faced by these 3D devices, focusing first on the impact of thermal and plasma treatments at gate module [6]. JG and noise can be substantially reduced, without EOT penalty, with a post HfO2 deposition anneal (PDA) and F incorporation in the gate stack by SF6. The latter can also improve the mobility and reduce Nit, mitigating the impact of fin patterning, fin corners and fin sidewalls crystal orientations, while also allowing a simplified dual-effective work-function (EWF) metal CMOS scheme where optimized cleans are key. PDA improves the bias-temperature-instability lifetime and hot-carrier immunity via reduction of bulk defects. Furthermore, the doping scheme and EWF metal can also be used to engineer the interface properties. Indeed, improved reliability and LF noise have been reported for junctionless (JL) GAA-NWFETs [4], with SVG.f of inversion-mode (IM) GAA-NWFETs showing more uniform oxide trap density profiles, as a function of depth, for TiAl-based vs. TiN EWF metals [7]. Extensionless IM or JL can also help to enlarge process robustness by ensuring a smaller Eox increase at the bottom-gate edges from the fins release process for lateral GAA-NWFETs formation [4]. These devices are closer to finFETs regarding layout and processing, but vertically stacked lateral NWs will be needed for them to be competitive in performance per footprint, with the drawback of increased parasitic capacitances [3]. Scaling is also being challenged as conventional 2D cell layouts are reaching the physical limits on gate and contact placement and facing interconnect routing congestion. Though requiring a more disruptive technological and design transition, vertical GAA-NWFETs appear particularly well placed to overcome some of these limitations and open up new scaling paths by fully using the third dimension [5]. Their gate length is defined vertically and hence can be relaxed without area penalty and used as a knob for variability control and optimized system performance. In this work, we tackle some of the integration challenges in surface definition for these devices, focusing on a channel-first approach. The vertical NWs (pillars) are defined by 193nm immersion lithography followed by dry-etch and wet treatments depending on the channel material employed. For NW doping, up to three stacked layers of (doped) epi are used, requiring pillar etch processes less sensitive to wide doping ranges. For Si NWs, using P doping for NMOS and B for PMOS, an optimized F-based plasma is used to yield arrays of high aspect-ratio pillars with diameters (dNWs) down to ~20nm (from ~42nm after litho). Further dNW reduction can be obtained by applying n cycles of low-temperature [O3-oxidation → oxide etch] for Si-based pillars, digital etch for III-V pillars [8]. Several alternative etch schemes are used for defining the layers surrounding the NWs, overcoming dry and wet etch-layout dependences. A replacement metal gate scheme can enable decoupling the gate module from doping/series resistance optimization for the top part of the pillars, where a highly doped epi layer can be grown for improved contacting (larger contact area). Removal of the dummy gate dielectric from the vertical channel is challenged by the presence of the layer(s) covering the top part of the pillars, selectivity requirements towards the bottom and top isolation layers, and, increasingly so for smaller dNWs, by metrology. A siconi-based oxide etch followed by a wet treatment is used prior to gate stack deposition, with a smoother gate electrode (with W fill-metal) easier to obtain than in a gate-first flow [5].

The Impact of Dummy Gate Processing on Si-Cap-Free SiGe Passivation: A Physical Characterization Study on Strained SiGe 25% and 45%

Si-cap-free SiGe passivation suffers from the potential presence of Ge-oxide in the interlayer prior to high-k deposition. Most of the advanced transistor designs use a replacement metal gate (RMG) integration scheme. The evolution of the Ge-content in the chemical oxide formed on SiGe channels with [Ge] = 25 and 45% was followed after the oxidation of pristine SiGe and compared to SiGe that was exposed to a short-loop flow mimicking an RMG integration scheme. The Ge content of the chemical oxide and SiGe virtual substrate was found to be strongly dependent on the spike anneal temperature. Also the roughness of the interlayer was found to increase. The impact of a TMAH-based clean prior to chemical oxide formation was also studied. Finally, the observations are explained qualitatively as a combination of the behavior for Si and Ge.

(Invited) Gate-All-Around Transistors Based on Vertically Stacked Si Nanowires

We report on gate-all-around (GAA) N- and P-MOSFETs made of 8-nm-diameter vertically stacked horizontal Si nanowires (NWs). We show that these devices, which were fabricated on bulk Si substrates using an industry-relevant replacement metal gate (RMG) process, have excellent short-channel characteristics (SS = 65 mV/dec, DIBL = 42 mV/V for LG = 24 nm) at performance levels comparable to FinFET reference devices. Furthermore, CMOS integration of GAA MOSFETs is demonstrated. Threshold voltage tuning is achieved by nanowire-compatible dual-work-function metal integration.

CMP: Consideration of Stop-on Selectivity in Advanced Node Semiconductor Manufacturing Technology

In advanced node semiconductor manufacturing, Chemical Mechanical Polish (CMP) is a critical process step in formation of many modules, from fin formation, replacement metal gate (RMG), Self-Aligned Contact (SAC), to interconnect. In each application, CMP’s stop-on capability is increasingly seen as an essential element in gauging device integrity, and thus is critical to the successful implementation of a technology. This presentation discusses the critical importance of CMP selectivity, how selectivity is measured and modulated, and how the need of stop-on capability is balanced with the need to make sure complete residue clearing.

CMP: Consideration of Stop-on Selectivity in Advanced Node Semiconductor Manufacturing Technology

In advanced node semiconductor manufacturing, Chemical Mechanical Polish (CMP) is a critical integration step to many modules, from fin formation, replacement metal gate (RMG), to interconnects. In each application, CMP’s stop-on capability is increasingly seen as an essential element in gauging device integrity, and thus is critical to the successful implementation of a technology. Traditionally, CMP selectivity is merely a characteristic of slurry chemistry and its abrasive materials, and is measured by blanket rates of the corresponding films. However, in advanced node semiconductor manufacturing, as feature sizes are at Nano scale and polishing precision needs to be controlled at angstrom level, this slurry selectivity does not necessarily translate to a good stop-on capability. At this precision level, stop-on performance is sensitive to the selection of CMP pad as well as how the CMP process is developed. It is also highly sensitive to the integration process, including the deposition process and various integration steps leading to CMP. This presentation reviews the critical roles CMP plays in fin formation, replacement metal gate (RMG) and local interconnects. Taking middle of line (MOL) CMP steps as examples, detailed discussion will be presented on how selectivity is modulated and how the needs of stop-on capability is balanced with the need to make sure complete clearing.

(Invited) Gate-All-Around Transistors Based on Vertically Stacked Si Nanowires

Gate-all-around (GAA) transistors based on vertically stacked horizontal nanowires are promising candidates to replace FinFETs in future CMOS technology nodes. First of all, GAA devices provide optimal electrostatic control over semiconducting nanowire channels, which enables downscaling of the gate length to below the FinFET limit, while maintaining low off-state leakage [1]. Besides, horizontally oriented nanowires are an evolutionary extension of FinFETs, as opposed to vertical nanowires which require more disruptive technology and design changes [2]. Finally, stacking of nanowires is relevant for enhancing the drive current per footprint. Based on these considerations, GAA transistors made of vertically stacked horizontal nanowires have been included in the ITRS roadmap to reduce the contacted gate pitch, which is a key figure of merit for CMOS device density, to below ~40 nm in 2019-2021 [3]. In the context of the industrial relevance described above, we present the fabrication of Si GAA devices on bulk Si substrates. Multiple processing aspects that are relevant for bulk CMOS technology definition are addressed, including stacking of 8-nm-diameter Si wires at 45-nm lateral pitch and 20-nm vertical pitch [4], and nanowire-compatible replacement metal gate processing in combination with threshold voltage tuning by dual work function metal integration [5]. Temperature restrictions for the formation of shallow trench isolation, and the interaction between N- and P-type junction formation on one hand and nanowire release processes on the other hand are discussed as well. [1] K. J. Kuhn, IEEE Trans. Electron Devices, vol. 59 (7), p.1813, (2012). [2] L. Liebmann et al., VLSI Tech. Dig., p.112 (2016). [3] The International Roadmap for Semiconductors (ITRS) 2.0, http://www.itrs2.net/ (2015). [4] H. Mertens et al., VLSI Tech. Dig., p.158 (2016). [5] H. Mertens et al., IEDM Tech. Dig., p.524 (2016). Figure 1

Effect of Reactive Ion Etch on the Polishing Selectivity during Silicon Nitride Chemical Mechanical Polishing for Sub-10 nm Logic Device

Silicon nitride (SiN) Chemical Mechanical Polishing (CMP) was adopted to create a metal gate capped with dielectric material (SiN) for self-aligned contact (SAC) processing in replacement metal gate (RMG) procedures for the development of sub-10 nm logic devices. Based on the sub-10 nm device integration scheme, SiN CMP removes SiN film and stops on an oxide layer. Therefore it requires high selectivity between SiN and oxide film. The SiN CMP slurries developed for this purpose, show more than 30:1 SiN removal selectivity to oxide from the blanket wafers. However, the selectivity from the pattern wafers is less than 3:1. This study investigates the selectivity difference between blanket wafer and pattern wafer. For pattern wafers, the process flow includes reactive ion etching to recess tungsten metal gates. During this process, the oxide properties are changed. X-ray Photoelectron Spectroscopy (XPS) was used to analyze the film property after reactive ion etching. Depending on etch conditions, polishing removal selectivity is sensitively influenced. The etch process effect on CMP selectivity was investigated in this study.

DC and RF characterization of InGaAs replacement metal gate (RMG) nFETs on SiGe-OI FinFETs fabricated by 3D monolithic integration

We report the first RF characterization of short-channel replacement metal gate (RMG) InGaAs-OI nFETs built in a 3D monolithic (3DM) CMOS process. This process features RMG InGaAs-OI nFET top layer and SiGe-OI fin pFET bottom layer. We demonstrate state-of-the-art device integration on both levels. The bottom layer SiGe-OI pFETs are fabricated with a Gate-First (GF) process with fins and featuring epitaxial raised source drain (RSD) as well as silicide contact layer. The top layer InGaAs nFETs are fabricated with a RMG process featuring a self-aligned epitaxial raised source drain (RSD). We show that the 3D monolithic integration scheme does not degrade the performance of the bottom SiGe-OI pFETs owing to an optimized thermal budget for the top InGaAs nFETs. From the RF characterizations performed (post-3D monolithic process) on multifinger-gate InGaAs-OI nFETs, we extract a cut-off frequency (Ft) of 16.4GHz at a gate-length (Lg) of 120nm. Measurements on various gate lengths shows increasing cut-off frequency with decreasing gate-length.