Material lattice orientation effect of local Si1-xGex stressors on the width dependence of high-k metal gate PMOSFETs

Abstract

The novel material selection and fabrication became a major concern due to scaling limitations when the technology node was below 20 nm. Complex gate-last process step for high-k metal gate (HKMG) device was proposed to enhance device mobility gain through the proper assistance of boosting channel stress. However, the impact of anisotropic material behavior regarding SiGe and silicon device is rarely estimated. Thus, the foregoing mechanical responses combined with concerned device layout during gate etch, replacement metal gate must be investigated. In this study, a process-oriented simulation methodology was presented to investigate this critical issue by a vehicle of 20 nm short-channel HKMG p-type MOSFET with embedded SiGe alloy stressor. Results indicated that the poly gate etch process significantly improved the longitudinal channel stress (Sxx) of this device channel. Process-induced Sxx values of −306.94 and −1325.48 MPa were obtained when the gate-first and gate-last processes were estimated, and 100 nm gate width was achieved, respectively. Given the increase in gate widths from 100 nm to 4000 nm, the maximum carrier mobility of 116.57% and 111.01% were obtained when isotropic and anisotropic material properties were adopted.