Effect of Reactive Ion Etch on the Polishing Selectivity during Silicon Nitride Chemical Mechanical Polishing for Sub-10 nm Logic Device

Abstract

Silicon nitride (SiN) Chemical Mechanical Polishing (CMP) was adopted to create a metal gate capped with dielectric material (SiN) for self-aligned contact (SAC) processing in replacement metal gate (RMG) procedures for the development of sub-10 nm logic devices. Based on the sub-10 nm device integration scheme, SiN CMP removes SiN film and stops on an oxide layer. Therefore it requires high selectivity between SiN and oxide film. The SiN CMP slurries developed for this purpose, show more than 30:1 SiN removal selectivity to oxide from the blanket wafers. However, the selectivity from the pattern wafers is less than 3:1. This study investigates the selectivity difference between blanket wafer and pattern wafer. For pattern wafers, the process flow includes reactive ion etching to recess tungsten metal gates. During this process, the oxide properties are changed. X-ray Photoelectron Spectroscopy (XPS) was used to analyze the film property after reactive ion etching. Depending on etch conditions, polishing removal selectivity is sensitively influenced. The etch process effect on CMP selectivity was investigated in this study.