Recess Channel Research Articles

Emerging Fluorite‐ and Wurtzite‐Type Ferroelectrics: From (Hf,Zr)O2 to AlN and Related Materials

Emerging Fluorite‐ and Wurtzite‐Type Ferroelectrics: From (Hf,Zr)O₂ to AlN and Related Materials

High‐Performance and High‐Endurance HfO2‐Based Ferroelectric Field‐Effect Transistor Memory with a Spherical Recess Channel

Owing to their high scalability and superior complementary metal–oxide–semiconductor (CMOS) compatibility, HfO2‐based ferroelectric field‐effect transistors (FeFETs) are proved to be promising candidates for emerging nonvolatile memory devices. However, the poor endurance of these FeFETs, which is attributed to the degradation of the interfacial dielectric layer, is a serious obstacle for commercialization. In FeFETs with a metal–ferroelectric–insulator–semiconductor gate stack, the strong electric field across the interfacial dielectric layer mainly induces charge injection/trapping and limits endurance to <106 cycles. Herein, optimum condition of switching polarization () of ferroelectric materials and a new structural approach to reduce the strength of the electric field across the interfacial dielectric layer and improve memory window (MW) and reliability properties are presented. Based on numerical simulation, it is found that an interfacial electric field increases with , and a metal–ferroelectric–metal–insulator–semiconductor FeFET with a 3D channel structure is effective to have high ratio of dielectric capacitance to ferroelectric capacitance, resulting in low electric field through the interfacial layer and large MW.

Improved Current Collapse in Recessed AlGaN/GaN MOS-HEMTs by Interface and Structure Engineering

Enhancement-mode (E-mode) GaN MOS-HEMTs using recess process typically face the challenge of precise thickness control, surface roughness issue, and interface traps, all of which could lead to the degradation of the device performance and cause reliability issues. In this article, we use a combined process of atomic layer etching (ALE) technique and atomic layer deposited (ALD) HfSiO dielectric. ALE is repeated oxidation and dry etching process with minimal surface damage, leading to a precisely controlled low-damage recess channel area. The fabricated AlGaN/GaN MOS-HEMTs exhibit E-mode operation with a positive threshold voltage ( ${V}_{\text {th}}$ ) of +2.1 V with small ${V}_{\text {th}}$ dispersion for different devices, an ultrahigh drain current ON– OFF ratio over 1010 and a low ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}}$ ) of $11.5~\Omega \cdot \text {mm}$ at gate-to-drain length ( ${L}_{\text {GD}}$ ) of $25~\mu \text{m}$ . Source field plate (SFP) structure is employed to reduce the charge trapping process and improve the reliability at high voltages. The current collapse of the E-mode device with SFP structure can be effectively suppressed due to the optimized redistribution of the peak electric field in the gate-to-drain access region, where a significantly improved dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of only 1.17 times increase from the static ${R}_{ \mathrm{\scriptscriptstyle ON}}$ after OFF-state ${V}_{\text {DS}}$ stress of 600 V. Moreover, the enhanced vertical electric field with decreased AlGaN barrier thickness and the positive shift in threshold voltage for the E-mode device can effectively suppress the current collapse, which outperforms the depletion-mode counterpart. The breakdown voltage reaches a considerable value of 1560 V at an OFF-state current density of ${1}~\mu \text{A}$ /mm.

Wafer-Scale Fabrication of Recessed-Channel PtSe2 MOSFETs With Low Contact Resistance and Improved Gate Control

Wafer-scale fabrication of PtSe2 MOSFETs was demonstrated by photolithography on Pt films directly selenized at 400 °C. Taking advantage of the unique property of PtSe2 to transition from a semiconductor to a semimetal as its thickness increases beyond a few monolayers, channel recess was adapted for improving gate control while keeping the contact resistance below 0.01 $\Omega \cdot \text {cm}$ . The wafer-scale fabrication resulted in uniform device characteristics so that average instead of best results was reported. For example, the drain currents at ${V}_{\text {GS}} = -10$ V, ${V}_{\text {DS}} = -1$ V were $25~\pm ~5$ , 57 ± 8, and $618~\pm ~17~\mu \text{A}/\mu \text{m}$ for 4-, 8-, and 12-nm-thick PtSe2, respectively. The corresponding peak transconductances were 0.20 ± 0.1, 0.60 ± 0.05, and $1.4~\pm ~0.1~\mu \text{S}/\mu \text{m}$ . The forward-current cutoff frequency of 12-nm-thick PtSe2 MOSFETs was 42 ± 5 MHz, whereas the corresponding frequency of maximum oscillation was 180 ± 30 MHz. These results confirmed the application potential of PtSe2 for future-generation thin-film transistors.

Improvement by Channel Recess of Contact Resistance and Gate Control in Large-Scale Spin-Coated MoS2 MOSFETs

Solution-processed 2-D materials, being low temperature, low cost, and scalable, are attractive for future-generation thin-film and flexible transistors. However, it is challenging to dispense solution-processed 2-D material into a thin and continuous channel for effective and uniform gate control. In addition, a thick channel under the source and drain contacts is required to increase the transfer length and decrease the edge contact resistance. To overcome such a dilemma and to obtain the optimum combination of effective gate control and low contact resistance, channel recess was demonstrated for the first time on MoS2, so that the channel is thin in the gate region but thick in the source and drain regions. Specifically, channel recess by CHF3/O2 dry etching up to 60 s was performed on submicron buried-gate MOSFETs fabricated on 20-nm-thick spin-coated MoS2. It was found that the channel recess improved the current on/off ratio by 3 orders of magnitude while maintaining approximately the same contact resistance and peak transconductance as that of a uniformly 20-nm-thick channel. The resulted performance was among the best of all solution-processed MoS2 MOSFETs. The same channel recess technique can be used to improve the performance of MOSFETs made of other solution-processed 2-D materials.

Characteristics of Recess Structure Tunneling Field Effect Transistor for High on Current Drivability

A novel tunneling field effect transistor (TFET) with a recess channel is proposed. Proposed TFET has a thin intrinsic region and it is formed in the shape of surrounding the gate. The performance of the proposed device is analyzed through comparison with double gate thin intrinsic TFET (DGTI) TFET and double gate (DG) TFET structures. The comparison results of on-current (ISUBon/SUBSUB/SUB) and subthreshold swing (S) with other devices shows that the proposed device has excellent characteristics. The effects of the structural parameters change of the device on the proposed device are analyzed and compared with the other two TFET structures. A guideline for the optimization of the proposed device is suggested.

Reliability Issues of In2O5Sn Gate Electrode Recessed Channel MOSFET: Impact of Interface Trap Charges and Temperature

In this paper, reliability issues of In2O5Sn (indium–tin oxide: a transparent material) transparent gate recessed channel (TGRC)-MOSFET has been analyzed by considering the effect of interface trap charges (both positive and negative) present at the Si/SiO2 interface. Following device, characteristics are studied in terms of static, linearity, and intermodulation figure of merits. It is found that with the amalgamation of the transparent gate indium tin oxide on conventional recesses channel (CRC) MOSFET, it exhibits improved immunity against interface trap charges in comparison to CRC-MOSFET. In addition, the influence of ambient temperature (150–300 K) along with trap charges on TGRC-MOSFET has also been explored with an aim to analyze at which temperature of the device is more stable in the presence of interface defects (trap charges). Results obtained reveal that TGRC shows improved device performance at low temperature with trap charges being less influenced. Thus, this paper demonstrates that TGRC MOSFET can act as a promising candidate for low-power linear analog applications, where low temperature is required.

High-Performance Recessed-Channel Germanium Thin-Film Transistors via Excimer Laser Crystallization

This letter demonstrates the excimer laser crystallization (ELC) of germanium (Ge) thin films with the recessed-channel (RC) structure for high-performance p-channel Ge thin-film transistors (TFTs). Using ELC, large longitudinal grains with a single perpendicular grain boundary (GB) in the center of the recessed region were formed. This can be attributed to the lateral grain growth from un-melted Ge solid seeds in the thick region toward the complete melting recessed region during ELC. Consequently, the proposed p-channel RC-ELC Ge TFTs possessing large longitudinal grains without the perpendicular GB in the channel region exhibited a superior field-effect hole mobility of 447 cm2V−1s−1 with minor performance deviation.

Comparing a hydrodynamic model from fifth generation DTM data and a model from data modified by means of CroSolver tool

Basic input into the hydrodynamic models is represented by altimetry data. One of ways to obtain such data is through the method of aerial laser scanning (ALS) from the digital relief model (DRM). This method is considered one of the most accurate methods for obtaining altimetry data. Its bottleneck is however incapacity of recording terrain geometry under water surface due to the fact that laser beam is absorbed by water mass. The absence of geometric data on watercourse discharge area may perceptibly affect results of modelling, especially if a missing part of the channel represents a significant discharge area with its capacity. One of methods for eliminating the deficiency is a sufficient channel recess by means of software tools such as CroSolver. The submitted paper deals with the construction of a hydrodynamic model using 5 th generation DRM data, and compares outputs from this model at various discharges with a model based on the altimetry data modified by using the CroSolver tool. Outputs from the two hydrodynamic models are compared in HEC-RAS programme with the use of recessed data and with the use of unmodified DRM. The comparison is done on the sections of two watercourses with different terrain morphology and watercourse size. A complementary output is the comparison of inundation areas issuing from both model variants. Our results indicate that differences in the outputs are significant, namely at lower discharges (Q1, Q5), whereas at Q50 and Q100 the difference is negligible with a great role played by the morphology of the modelled area and by the watercourse size.

DRAM Weak Cell Characterization for Retention Time.

This work proposes a sequence of tests for detecting refresh weak cells based on data retention time distribution in the main cell array of DRAMs and verify the feasibility of the proposed method through analysis of 30 nm design-rule DRAM cells with Recess Channel Array Transistor (RCAT) and Buried Channel Array Transistor (BCAT). Basic idea of the proposed mechanism is to test with different bias conditions and break down retention failures based on their root causes such as Gate Induced Drain Leakage, sub-threshold leakage and junction leakage. This categorization helps to determine the physical locations of each failure group, enabling precise Physical Failure Analysis (PFA). The characterization of data retention weak cells for 30 nm design rule DRAMs with BCAT and RCAT has been investigated. Most weak cells were classified as GIDL leaky cells in both cases. In the case of BCAT, the distance between the word line and the storage node, caused by the process distribution, is the main origin of weak cells. In the case of RCAT, the sharp corner of the active layer in the storage node is the main cause of weak cells.

Germanium nMOSFETs With Recessed Channel and S/D: Contact, Scalability, Interface, and Drain Current Exceeding 1 A/mm

A novel recessed channel and source/drain (S/D) technique is employed in Ge nMOSFETs, which greatly improves metal contacts to n-type Ge with contact resistance of down to 0.23 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega \cdot {\rm mm}$ </tex-math></inline-formula> and enhances gate electrostatic control with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\rm ON} / I_{\rm OFF}$ </tex-math></inline-formula> of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&gt; 10^{5}$ </tex-math></inline-formula> . The recessed S/D contacts are thoroughly investigated, showing strong dependence on the doping profile. For the first time, the drain current of Ge nMOSFETs has exceeded 1 A/mm with an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{d}$ </tex-math></inline-formula> of 1043 mA/mm on a 40-nm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L_{\rm ch}$ </tex-math></inline-formula> device. Scalability study is carried out in deep sub-100-nm region on Ge nMOSFETs with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L_{\rm ch}$ </tex-math></inline-formula> down to 25 nm. Interface study is also conducted with a new postoxidation method introduced, which significantly reduces the interface trap density. Device behaviors corresponding to interface traps are also investigated through a Technology Computer Aided Design simulation.

Complementary-Metal–Oxide–Semiconductor Technology-Compatible Tunneling Field-Effect Transistors with 14 nm Gate, Sigma-Shape Source, and Recessed Channel

A new design of tunneling field-effect transistor (TFET) focusing on the compatibility to the current Si complementary-metal–oxide–semiconductor (CMOS) technology is proposed. In addition to use of the structural components of the state-of-the-art CMOS technologies, such as Σ-shaped embedded SiGe and the replacement gate techniques, two-step sidewall image transfer gate-patterning and channel recess process are adopted to form highly-scaled nanoscale TFET. Process integration scheme and the expected device characteristics are examined on the basis of technology computer-aided design (TCAD) simulation on 14-nm-gate model devices. Tunability of transfer characteristics with doping around tip region, control of short-channel effect with channel recess, and improvement of current drivaility with SiGe composition are studied. Design of the source region is found to be critical in controlling the current drivability of the device and output characteristics.

Dependence of DRAM Device Performance on Passivation Annealing Position in Trench and Stack Structures for Manufacturing Optimization

The dependence of dynamic random access memory (DRAM) device performance on trench and stack cell structures was first observed by changing the process position of passivation annealing. For the trench DRAM, the data retention fail bit counts (FBCs) decreased by 18% and the cell transistor threshold voltage (CTVth) shift by 53 mV. The FBCs are primarily influenced by the junction leakage current. In contrast, for the stack DRAM, the data retention FBCs increased by 225% and the CTVth shift increased by 20 mV. The FBCs are primarily influenced by the gate-induced drain leakage (GIDL) current because of the large gate and the drain overlap region in the recess channel array transistor (RCAT). The interface states increased after the deposition of the plasma nitride layer, as observed in the charge pumping measurement in the trench DRAM. Transmission electron microscopy indicated that the gate oxide thickness in the bottom region of the RCAT is thinner to generate gate oxide leakage. Furthermore, a decrease in the activation energy from 0.64 to 0.55 eV implies the occurrence of GIDL current, which corresponds to the FBC analysis result. This paper demonstrated that the passivation annealing position requires careful adjustment for device and manufacturing optimization.

High-Performance Excimer-Laser-Crystallized Polycrystalline Silicon Thin-Film Transistors with the Pre-Patterned Recessed Channel

High-performance polycrystalline silicon (poly-Si) thin-film transistors (TFTs) have been achieved using an excimer laser crystallization method on a prepatterned recessed channel (RC). Such a prepatterned RC TFT exhibited an excellent field-effect mobility of 412 cm2 V-1 s-1 and an on/off current ratio higher than 1.1×108 as compared with 125 cm2 V-1 s-1 and 2.2×107 for the conventional ones, respectively. This is attributed to the two-dimensional control of the grain boundary location and the resultant cross-shaped grain boundary structures within the recessed regions. Therefore, the prepatterned RC TFTs with only one grain boundary parallel to the channel direction as the TFTs could be fabricated to avoid the perpendicular grain boundary. This technology is thus promising for the future applications of poly-Si TFTs in the system-on-panel (SOP) and three-dimensional integrated circuits (3D-ICs).

A Novel SONOS Memory With Recessed-Channel Poly-Si TFT via Excimer Laser Crystallization

A silicon-oxide-nitride-oxide-silicon memory with recessed-channel (RC) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) via excimer laser crystallization (ELC) has been demonstrated to achieve a high mobility of ~ 400 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V · s and a large ON/OFF current ratio of ~ 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> . Such a high performance is because the RC poly-Si TFTs possess only one perpendicular grain boundary (GB) in the channel and the corresponding protrusion at this GB. In addition, the proposed devices also exhibited the largest memory window of 2.63 V in 10 ms with respect to 2.37 and 1.31 V for the conventional-ELC and solid-phase-crystallized ones, respectively. Since the silicon grain growth could be artificially controlled, the device-to-device uniformity could be significantly improved. Therefore, such a simple scheme is promising for applications of low-temperature poly-Si TFTs in 3-D ICs and system on panel.

Measurement of mechanical stresses induced by hybrid shallow-trench-isolation for dynamic random access memory using recess channel array transistor structure

Methods of measuring mechanical stresses which are induced by hybrid shallow-trench-isolation (STI) for dynamic random access memories (DRAMs) using recess channel array transistor (RCAT) structure, are investigated. The STI was fabricated using high-density-plasma chemical-vapor-deposition (HDP-CVD) and spin-on-glass (SOG) processes. The mechanical stress at the channel region was evaluated using the subthreshold current method, and mechanical stress at the drain region was evaluated using the gate induced drain leakage current method which is proposed in this paper. Experimental results show that the SOG bottom layer induced a biaxial tensile stress in the range of 70.26-399.2MPa, while the HDP-CVD SiO2 top layer induced a biaxial compressive stress in the range of 0.220-7.291GPa. The mechanical stress varied the data retention time tret for the RCAT-structure DRAM by ~67.1%. tret had a strong correlation with the biaxial tensile stress, but had little correlation with the biaxial compressive stress.

Nanoscale Two-Bit/Cell NAND Silicon-Oxide-Nitride-Oxide-Silicon Devices with a Separated Double-Gate Saddle-Type Structure

Nanoscale two-bit/cell NAND silicon-oxide-nitride-oxide-silicon flash memory devices based on a separated double-gate (SDG) saddle structure with a recess channel region had two different doping regions in silicon-fin channel to operate two-bit per cell. A simulation results showed that the short channel effect, the cross-talk problem between cells, and the increase in threshold voltage distribution were minimized, resulting in the enhancement of the scaling-down characteristics and the program/erase speed.

Random Telegraph Signal-Like Fluctuation Created by Fowler–Nordheim Stress in Gate Induced Drain Leakage Current of the Saddle Type Dynamic Random Access Memory Cell Transistor

We generated traps inside gate oxide in gate–drain overlap region of recess channel type dynamic random access memory (DRAM) cell transistor through Fowler–Nordheim (FN) stress, and observed gate induced drain leakage (GIDL) current both in time domain and in frequency domain. It was found that the trap inside gate oxide could generate random telegraph signal (RTS)-like fluctuation in GIDL current. The characteristics of that fluctuation were similar to those of RTS-like fluctuation in GIDL current observed in the non-stressed device. This result shows the possibility that the trap causing variable retention time (VRT) in DRAM data retention time can be located inside gate oxide like channel RTS of metal–oxide–semiconductor field-effect transistors (MOSFETs).

Analytic Threshold Voltage Model of Recessed Channel MOSFETs

Threshold voltage is one of the most important factors in a device modeling. In this paper, analytical method to calculate threshold voltage for recessed channel (RC) MOSFETs is studied. If we know the fundamental parameter of device, such as radius, oxide thickness and doping concentration, threshold voltage can be obtained easily by using this model. The model predicts the threshold voltage which is the result of 2D numerical device simulation.

Modeling of Polysilicon Depletion Effect in Recessed-Channel MOSFETs

The polysilicon depletion effect is one of the key factors that degrade MOSFETs' performance. In this letter, a polysilicon depletion model for recessed-channel (RC) MOSFETs is presented. The model shows good agreement with numerical device simulation results. We also compare the polysilicon depletion effect of RC MOSFETs to that of planar MOSFETs.