Abstract
A novel recessed channel and source/drain (S/D) technique is employed in Ge nMOSFETs, which greatly improves metal contacts to n-type Ge with contact resistance of down to 0.23 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega \cdot {\rm mm}$ </tex-math></inline-formula> and enhances gate electrostatic control with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\rm ON} / I_{\rm OFF}$ </tex-math></inline-formula> of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$> 10^{5}$ </tex-math></inline-formula> . The recessed S/D contacts are thoroughly investigated, showing strong dependence on the doping profile. For the first time, the drain current of Ge nMOSFETs has exceeded 1 A/mm with an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{d}$ </tex-math></inline-formula> of 1043 mA/mm on a 40-nm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L_{\rm ch}$ </tex-math></inline-formula> device. Scalability study is carried out in deep sub-100-nm region on Ge nMOSFETs with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L_{\rm ch}$ </tex-math></inline-formula> down to 25 nm. Interface study is also conducted with a new postoxidation method introduced, which significantly reduces the interface trap density. Device behaviors corresponding to interface traps are also investigated through a Technology Computer Aided Design simulation.
Published Version
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