Abstract

We generated traps inside gate oxide in gate–drain overlap region of recess channel type dynamic random access memory (DRAM) cell transistor through Fowler–Nordheim (FN) stress, and observed gate induced drain leakage (GIDL) current both in time domain and in frequency domain. It was found that the trap inside gate oxide could generate random telegraph signal (RTS)-like fluctuation in GIDL current. The characteristics of that fluctuation were similar to those of RTS-like fluctuation in GIDL current observed in the non-stressed device. This result shows the possibility that the trap causing variable retention time (VRT) in DRAM data retention time can be located inside gate oxide like channel RTS of metal–oxide–semiconductor field-effect transistors (MOSFETs).

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