Enhancement of DRAM Performance by Adopting Metal–Interlayer–Semiconductor Source/Drain Contact Structure on DRAM Cell

Abstract

The effects of a metal–interlayer–semiconductor (MIS) source/drain (S/D) contact structure on a dynamic random access memory (DRAM) cell transistor are investigated using 3-D technology computer-aided design simulation. When the MIS S/D contact structure is used in a DRAM cell, the retention time increases by approximately 16.22 times when compared with that of the device using the metal–semiconductor (MS) S/D contact structure owing to the lowered S/D doping concentration, leading to a decrement of the gate-induced drain leakage. Furthermore, the write time and charge-sharing time, respectively, are approximately 0.74 and 0.69 times shorter when compared with the device using the MS S/D contact structure owing to better ohmic characteristics, which increase the drain current during the write/read operations. Thus, the MIS S/D contact structure can effectively enhance the retention and write/read characteristics of a DRAM cell, and it can be a promising S/D contact alternative for the DRAM cell in the sub-2y-nm technology node.