Abstract
This work proposes a sequence of tests for detecting refresh weak cells based on data retention time distribution in the main cell array of DRAMs and verify the feasibility of the proposed method through analysis of 30 nm design-rule DRAM cells with Recess Channel Array Transistor (RCAT) and Buried Channel Array Transistor (BCAT). Basic idea of the proposed mechanism is to test with different bias conditions and break down retention failures based on their root causes such as Gate Induced Drain Leakage, sub-threshold leakage and junction leakage. This categorization helps to determine the physical locations of each failure group, enabling precise Physical Failure Analysis (PFA). The characterization of data retention weak cells for 30 nm design rule DRAMs with BCAT and RCAT has been investigated. Most weak cells were classified as GIDL leaky cells in both cases. In the case of BCAT, the distance between the word line and the storage node, caused by the process distribution, is the main origin of weak cells. In the case of RCAT, the sharp corner of the active layer in the storage node is the main cause of weak cells.
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