Measurement of mechanical stresses induced by hybrid shallow-trench-isolation for dynamic random access memory using recess channel array transistor structure

Abstract

Methods of measuring mechanical stresses which are induced by hybrid shallow-trench-isolation (STI) for dynamic random access memories (DRAMs) using recess channel array transistor (RCAT) structure, are investigated. The STI was fabricated using high-density-plasma chemical-vapor-deposition (HDP-CVD) and spin-on-glass (SOG) processes. The mechanical stress at the channel region was evaluated using the subthreshold current method, and mechanical stress at the drain region was evaluated using the gate induced drain leakage current method which is proposed in this paper. Experimental results show that the SOG bottom layer induced a biaxial tensile stress in the range of 70.26-399.2MPa, while the HDP-CVD SiO2 top layer induced a biaxial compressive stress in the range of 0.220-7.291GPa. The mechanical stress varied the data retention time tret for the RCAT-structure DRAM by ~67.1%. tret had a strong correlation with the biaxial tensile stress, but had little correlation with the biaxial compressive stress.