Read Disturbance Research Articles

A Novel 8T Cell-Based Subthreshold Static RAM for Ultra-Low Power Platform Applications

Subthreshold SRAMs profit various energy-constrained applications. The traditional 6T SRAMs exhibit poor cell stability with voltage scaling. To this end, several 8T to 16T cell designs have been reported to improve the stability. However, they either suffer one of disturbances or consume large bit-area overhead. Furthermore, some cell options have a limited write-ability. This paper presents a novel 8T static RAM for reliable subthreshold operation. The cell employs a fully differential scheme and features cross-point access. An adaptive cell bias for each operating mode eliminates the read disturbance and enlarges the write-ability as well as the half-select stability in a cost-effective small bit-area. The bit-cell also can support efficient bit-interleaving. To verify the SRAM technique, a 32-kbit macro incorporating the proposed cell was implemented with an industrial 180 nm low-power CMOS process. At 0.4 V and room temperature, the proposed cell achieves 3.6× better write-ability and 2.6× higher dummy-read stability compared with the commercialized 8T cell. The 32-kbit SRAM successfully operates down to 0.21 V (~0.27 V lower than transistor threshold voltage). At its lowest operating voltage, the sleep-mode leakage power of entire SRAM is 7.75 nW. Many design results indicate that the proposed SRAM design, which is applicable to an aggressively-scaled process, might be quite useful in realizing cost-effective robust ultra-low voltage SRAMs.

Investigation of Read Disturb and Bipolar Read Scheme on Multilevel RRAM-Based Deep Learning Inference Engine

The multilevel resistive random access memory (RRAM)-based synaptic array can enable parallel computations of vector–matrix multiplication for machine learning inference acceleration; however, any conductance drift of the cell may induce an inference accuracy drop because the analog current is summed up along the column. In this article, the read disturb-induced conductance drift characteristic is statistically measured on a test vehicle based on 2-bit HfO2 RRAM array. The drift behavior of four states is empirically modeled by a vertical and lateral filament growth mechanism. Furthermore, a bipolar read scheme is proposed and tested to enhance the resilience against the read disturb. The modeled read disturb and proposed compensation scheme are incorporated into a VGG-like convolutional neural network for CIFAR-10 data set inference.

Lateral charge migration induced abnormal read disturb in 3D charge-trapping NAND flash memory

Abnormal read disturb (RD) has been investigated in three-dimensional (3D) charge-trapping NAND flash memory. Similar to traditional 2D NAND, RD will cause more error bits right after programming. However, after short-time retention, it has weak effects on error bits; more importantly, after long-time retention, a part of error bits can be recovered. With special coding designs in chip characterizations and TCAD simulations, it is concluded that lateral charge migration could be dominant mechanism for abnormal RD, which can be utilized to prolong lifetime of 3D NAND-based memory system for cold storage applications.

ROCKY: A Robust Hybrid On-chip Memory Kit For The Processors With STT-MRAM Cache Technology

STT-MRAM is regarded as an extremely promising NVM technology for replacing SRAM-based on-chip memories. While STT-MRAM memories benefit from ultra-low leakage power and high density, they suffer from some reliability challenges, namely, read disturbance, write failure, and retention failure. The write failure; storing a wrong value in an STT-MRAM cell during a write operation, is the most crucial reliability challenge. In this article, we propose ROCKY; a robust architecture equipped with efficient replacement policies for STT-MRAM-based cache memory hierarchy to improve the robustness of STT-MRAM part against the write failures. ROCKY reduces susceptible transitions in STT-MRAM cache memories leading to more reliable STT-MRAM write operations. The simulation results through comparison with traditional cache memory hierarchy demonstrate ROCKY decreases the WER of STT-MRAM cache memories by up to 35.4 percent while imposing less than 1 percent performance overhead to the system.

A Dynamic Reference and Variation-Tolerant Sensing Circuit for Deep Nanometer STT-MRAM

STT-MRAM has received wide attention with its promising properties as the next generation memory. Over the years, with entering into nanometer technology, as process-temperature-voltage (PTV) variations being intensified increasingly, the read reliability of STT-MRAM becomes a critical problem. Therefore, it is highly required to design a sensing circuit with good sensing margin (SM) and anti-interference. This paper presents a dynamic reference (DR) and variation-tolerant sensing circuit for deep nanometer STT-MRAM. The circuit is composed with a clamp voltage generator (CVG), a dynamic reference generator (DRG), and a fully differential charge transfer amplifier (FDCTA). It is demonstrated that the proposed sensing circuit is capable of immunizing the PTV variations by increasing the sensing margin (SM) while lowering the read disturbance (RD). The sensing margin of the proposed circuit can be as high as 312 mV on condition of VDD to be 1.2 V and TMR value to be 150%.

Modeling of Voltage-Controlled Spin–Orbit Torque MRAM for Multilevel Switching Application

Magnetic tunnel junction (MTJ) has emerged as a viable candidate for next-generation memory and logic applications. Manipulation of the magnetic and electric field can control the spin and charge state variables that are of utmost importance in spintronics devices. In this article, the modeling of voltage-controlled spin–orbit torque (VCSOT)-based magnetic random access memory (MRAM) is demonstrated. VCSOT MRAM is an ultrafast device owing to a magnetic switching time of 0.7 ns. It is more energy-efficient as compared to spin–orbit torque (SOT) MRAM. VCSOT MRAM has been exemplified for multilevel cell (MLC) application to enhance the memory integration density. Two-bit serial MLC (sMLC) and parallel MLC (pMLC) designs are proposed using VCSOT MRAM. These MLCs are more energy-efficient as compared to SOT-MLCs. Moreover, 2-bit sMLC and pMLC VCSOT-MRAM significantly reduce average write energy by 91.5% and 49.6%, respectively, as compared to SOT-based MLC. Performance metrics for these devices have been illustrated, which shows the negligible read disturbance and write error rates.

Robust Offset-Cancellation Sensing-Circuit-Based Spin-Transfer-Torque Nonvolatile Flip-Flop

Nonvolatile flip-flop (NV-FF) based systems can be effectively implemented in battery-limited internet of things (IoT) applications due to their zero standby power consumption and instant ON/OFF characteristics. Among various NV-FFs, spin-transfer-torque magnetic tunnel junction based NV-FFs are the most applicable due to their nonvolatility, high endurance, complementary metal-oxide-semiconductor (CMOS) compatibility, scalability, and rapid sensing and write speed due to its low resistance. However, they are subject to a degraded sensing margin for restoring operation with technology shrinks because of the increased process variation and reduced supply voltage. This paper proposes a novel NV-FF with a significantly superior offset-tolerance and reduction in read current (I read ) that produces read disturbance in comparison to state-of-the-art NV-FFs. Monte Carlo HSPICE simulation results based on industry-compatible 65-nm model parameters revealed that the proposed NV-FF can achieve a three-order improvement in the restore yield and a two-order reduction in the I read when compared with state-of-the-art NV-FFs.

Novel MTJ-Based Sensing Inverter Variation Tolerant Nonvolatile Flip-Flop in the Near-Threshold Voltage Region

In recent years, the low power design of Internet of Things devices has become increasingly important. The most basic method to implement a low power design is to reduce static power consumption. In this regard, a spin-transfer-torque magnetic-tunnel-junction-based nonvolatile flip-flop (NVFF) is a promising candidate for storing the computing data while the power is off. However, as the technology node scales down, the process variation increases, leading to a restoration failure in previous NVFFs, especially in the near-threshold voltage (NTV) region. For better energy efficiency when operating the NVFF in the NTV region, this article presents a novel NVFF that guarantees a target restore yield of 4σ and a target read disturbance margin of 6σ in the NTV region (0.6 V supply voltage), along with auto-zeroing and dynamic reference voltage (DRV) techniques, using only a single capacitor to improve the NVFF's restore yield. The Monte Carlo HSPICE simulation results using industry-compatible 28-nm model parameters show that the proposed NVFF satisfies both the target restore yield and the read disturbance margin, saving 44% restoration time compared with the current state-of-the-art NVFF, which does not satisfy the target restore yield despite having offset cancellation characteristic.

Enhanced test algorithm for nanoelectronic Resistive Random Access Memory testing using self check write scheme

Emerging nanoelectronic memories such as PCRAM, STT-RAM, Ferroelectric FET Memory and Resistive Random Access Memory (RRAM) are proficient to substitute the traditional memory technologies such as SRAMs, DRAMs and flash memory in future computers. Among all these nanoelectronic memories RRAM (combines the merits of both RAM and Flash memories) is exceptionally fast, cost-effective which is capable of accomplishing the requirements of immense growth in data and storage. Despite the fact that it suffers by various faults, more specifically Write Disturbance Fault (WDF) and Read Disturbance Fault (RDF) has huge effect on system performance and reliability. Different algorithms are designed to identify specific kind of faults and the main drawback of all existing algorithm is redundancy (repeated March elements with write and read operations) it will increase the test complexity and time. Moreover, this repeated write and read operation will leads to endurance degradation. To circumvent this pitfall, a self-checking write circuit is adapted where the accuracy of every write operation is verified at the end of write cycle by means of a write verification signal in the write circuit (acts as in built read circuit). Hence, this self checking write method offers a combined “write and read” operation (wr) that detects the faulty write operation (main reason for read fault) and avoids the data corruption in memory system. To the best of our knowledge, we are the first one to propose March algorithm with “wr” element hence it is named as novel ‘March WR’ testing algorithm which detects WDF and RDF effectively with 4n test complexity which is very less than all other existing test algorithms. Thus it reduces 63.63% of the test time. Due to keen monitoring of each operation 100% fault coverage is achieved that results in enhanced performance and reliability.

Low Leakage SRAM Cell with Improved Stability for IoT Applications

Abstract For IoT applications, a new SRAM cell with differential write and single-ended read ability is proposed in this paper. The transmission gate is used as an access transistor to get rail to the rail voltage swing and improved stability. Analysis of leakage power and stability for proposed SRAM cell at supply voltage ranging from 0.9V to 0.5V is compared with the existing 5T and 6T SRAM bit cells at 32nm technology. The transistor stacking effect is used to minimize the leakage current of the SRAM cell. The stability increase is accomplished by isolating read line from the node that causes read disturbance problem. The proposed memory cell shows 436x and 1.15x improvement in read power in comparison to 6T and 5T cell, respectively at 0.8V supply voltage. Stability is also improved by 1.15x and 1.12x at 0.8V of supply voltage.

A Multilayer High-Speed Magnetic-Tunnel-Junction Magneto-resistive RAM Structure with Read-Disturb-Detection Circuit by Using Nano-Electronics Quantum Dot Cellular Method

In this nano technical world the “Complementary MOS technology” can be replaced by using “Quantum Dot Cellular Automata” with reversible logical phenomenon to achieve a fault tolerant, low-cost nano electronics formation by feature size, latency and power consumption minimization. The memory is one of the most interesting part of research in this digital world. This paper represents an optimizing high-frequency (in THz) reversible design of a “Random Access Memory” which is simulated by using nano electronics ‘QCA’ simulator to get a better performance than “Complementary MOS technology” with high frequency (in THz), less occupied area and dissipated power. This paper also shows a highly-flexible magnetic quantum cell logic-design and MTJ logical representation which is used for non-volatile MRAM which is widely used in digital electronics world and as a part of aerospace and military device. A reversible nano electronics formation of the control logic to select the word-line and input-line of the MRAM also presented here. The reversible-logic can avoid the information-loss in memory device by zero-heating technique. Non-reversible formations dissipate ‘KTln2’ energy per bit which can be ignored in reversible formation. But, read disturb at low write current is a major issue of MTJ MRAM due to the same path of read/write current path. In this paper a three dimension reversible “Read Disturb Detection Circuit” is formed by nano electronics ‘QCA’ technology which bit-wise follows the control logic of read-disturb-detection technique and the same figure also simulated by ‘VHDL’ coding in Xilinx software to prove the advantages of ‘QCA’ technology contrast to Xilinx This paper also focuses on the correspondence between change of temperature and supply power.

Mitigating and Tolerating Read Disturbance in STT-MRAM-Based Main Memory via Device and Architecture Innovations

As an important nonvolatile memory technology, spin transfer torque magnetoresistive RAM (STT-MRAM) is widely considered as a universal memory solution for future processors. Employing STT-MRAM as the main memory offers a wide variety of benefits, but also results in unique design challenges. In particular, read disturbance characterizes accidental data corruption in STT-MRAM after it is read, leading to the need of restoring data back to memory after each read operation. In this paper, we propose both device and architecture innovations to mitigate and tolerate read disturbance. First, we quantitatively demonstrate the relationship between read disturbance and key device parameters, conducting a number of read disturbance mitigation schemes. These device-level schemes turn out to be effective in reducing the read disturbance probability, but come with costs on other design metrics. Consequently, we further propose a restore-aware memory controller design at the architecture level to tolerate read disturbance. Since the extra restores incurred by read disturbance greatly change the timing scenarios that conventional memory controllers were optimized for, directly adopting restore-agnostic DRAM memory management techniques will lead to suboptimal designs for STT-MRAM. Therefore, we propose restore-aware policy selection (RAPS), a dynamic and hybrid row buffer management scheme that factors in the inevitable data restores in STT-MRAM-based main memory. RAPS monitors the row buffer hit rate at run time, dynamically switching between two static page-closure policies. By factoring in restores, RAPS accurately captures the optimal design points, achieving optimal policy selections at run time. Our experimental results show that RAPS significantly improves system performance and energy efficiency compared to conventional page-closure policies.

Analysis and optimization of read/write reliability for 12F2 cross-point ultra-fast phase change memory

Phase change memory (PCM) device using a diode as selector exhibits a high level of integration based on 40 nm process, but it still has some reliability problems, such as read disturbance and writing performance. In this paper, we test and improve the read/write reliability of one diode and one resistor (1D1R) structure cell in array with cell size of 12F2 (0.16 μm × 0.12 μm). The 1D1R device has good performance with ultra-high speed (20 ns) and low programming voltage (3.3 V). The cell programmed by current pulse has a better performance than that of voltage operation in amorphous state with respect to read disturb immunity. The ratio of reset/set resistance can be improved by choosing appropriate parameter of write operation. In addition, the endurance characteristics of the devices are investigated. The optimization in read/write operation guarantee that 1D1R device can satisfy the requirements for the high-speed and high-density applications.

Analysis on New Read Disturbance Induced by Hot Carrier Injections in 3-D Channel-Stacked NAND Flash Memory

Read disturbance is analyzed in vertically channel-stacked NAND flash memory, which has string select transistors (SSTs) to access each channel layer independently. Additional read disturbance is observed at the cells adjacent to the selected cell in the unselected channel layers as well as typical read disturbance caused by repetitive Fowler–Nordheim tunneling (F-N) stress. Technology computer-aided design simulations and measurements are performed to investigate the disturbance mechanisms. It is found that bitline-side [common-source line-side] adjacent cell is disturbed by the hot carrier injection (HCI), which results from positively [negatively] boosted channel potential by the rising [falling] of the voltage ( ${V}_{\text {unsel}}$ ) applied to unselected cells, respectively. A novel read operation, in which the selected cells are maintained in turned on state during the ${V}_{\text {unsel}}$ rising/falling and then are restored to their own states, is proposed to suppress the occurrence of the HCIs. As a result, it is revealed that the HCI-induced read disturbances are successfully suppressed by the proposed method.

An Adaptive Thermal-Aware ECC Scheme for Reliable STT-MRAM LLC Design

Considering the insatiable demand for high-performance computing, on-chip cache capacity increases rapidly. Spin-transfer-torque magnetoresistive random-access memory (STT-MRAM) is a promising cache candidate due to ultralow standby power, high-access speed, and integration density. Unfortunately, when the feature size of magnetic tunnel junction (MTJ) scales down to 1 Xnm, read current approaches write current closely, which may result in read disturbance threatening the reliability of STT-MRAM. Furthermore, the elevating on-chip temperature reduces the thermal stability of STT-MRAM remarkably and aggravates the read disturbance. Error correction code (ECC) is an effective technique to enhance memory reliability. In this paper, we take advantage of the thermal dependence of STT-MRAM and propose a thermally adaptive ECC design, called “Chameleon,” that can adjust the ECC protection strength dynamically to reduce the ECC storage overhead and improve the cache access performance and energy efficiency. Experimental results show that compared to the conservative nonadaptive ECC scheme, our design can improve both cache performance and energy consumption effectively.

A Restore-Free Mode for MLC STT-RAM Caches

Spin-transfer torque RAM (STT-RAM) caches are foreseen to replace traditional static RAM caches because of their nonvolatile nature and high density. Multilevel cell (MLC) STT-RAMs further enhance the storage density of single-level cell STT-RAMs. However, the two-step read/write process in MLC STT-RAMs adversely affects performance, energy consumption, and lifetime. Moreover, technology scaling makes the read operations disturb the stored data in MLC STT-RAMs, giving rise to an issue called read disturbance (RD). Restore operations, which are required to cope with RD, further add to the problems of using MLCs. In this brief, we propose a Restore-free mode for frequently reused cache lines in MLC STT-RAMs that leverages single-step read/write operations to the MLC without the need for restore operations. Our proposed scheme in single-core (quad-core) systems, achieves a 27.4% (23%) dynamic energy reduction, a 3.7% (7%) increase in performance, and an 81% (62.5%) lifetime improvement.

REACT: Read/Write Error Rate Aware Coding Technique for Emerging STT-MRAM Caches

Spin-transfer torque magnetic RAMs (STT-MRAMs) are the most promising alternative for static random-access memories in large last-level on-chip caches due to their higher density and near-zero leakage power. However, the reliability of STT-MRAMs is threatened by high probability of read disturbance and write failure . Both read disturbance and write failure, which cause a soft error in the cache cells, have an asymmetric behavior. Read disturbance occurs only in STT-MRAM cells storing “1” value, and write failure error rate in a $0\rightarrow 1$ transition is much higher than that in a $1\rightarrow 0$ transition. In this paper, we propose Read/write Error-rate Aware Coding Technique (REACT) to improve the reliability of the emerging STT-MRAM caches. REACT decreases the read disturbance and write failure rates by reducing the total number of “1”s and $0\rightarrow 1$ transitions on a cache block update. Our simulation results show that REACT reduces the probability of read disturbance and write failure up to 58% and 71%, respectively. These improvements are achieved by imposing negligible area, power, and performance overheads (less than 1%).

Thermoelectric Cooling Read for Resolving Read Disturb With Inrush Current Issue in OTS-PRAM

Phase change random access memory with ovonic threshold switch (OTS-PRAM) has been recently highlighted as an alternative to dynamic random access memory to meet the demand for memory capacity expansion in multicore processing. However, read disturb with inrush current (RDI) occurs owing to the snapback phenomenon caused by the threshold switching of the OTS selector in the OTS-PRAM cell, which should be resolved for realizing the practical use of OTS-PRAM. In this study, the RDI is analyzed in detail for the first time. Based on this analysis, a novel thermoelectric cooling read technique (TCR) that utilizes the thermoelectric effect in the storage material of the OTS-PRAM is proposed for effectively resolving the RDI issue. The proposed TCR is verified using the Sentaurus TCAD simulator, and a core structure with the proposed TCR is evaluated. HSPICE simulation results with a memory industry-compatible 0.25- μ m core circuit design rule for 20-nm PRAM technology show that the proposed TCR has a power gain of 67%, system performance improvement of 13.9%, and slight area overhead of 3% as compared to the SET-back write technique, which was the most promising technique for resolving the RDI issue until now.

Kanji (Morphogram) and Kana (Phonogram) Problem in Japanese Alexia and Agraphia.

The kanji and kana (or kanji vs. kana) problem in the Japanese language denotes the dissociation between kanji (morphograms) and kana (phonograms) in reading/comprehension and writing. Since paragraphia of kana in a patient with amyotrophic lateral sclerosis was first reported in 1893, kanji-kana dissociation has been the central topic in Japanese aphasiology. Recent advancements in lesion-to-symptom analyses and functional imaging studies have identified some areas whose damage causes dissociative disturbances of reading or writing between kanji and kana. That is, (1) angular alexia with agraphia causes kanji agraphia; alexia of kana with an angular gyrus lesion is the result of a damage to the middle occipital gyrus; (2) alexia with agraphia for kanji is caused by a posterior inferior temporal cortex (mid-fusiform/inferior temporal gyri; visual word form area) lesion, whereas pure agraphia for kanji is caused by a posterior middle temporal gyrus lesion; and (3) pure alexia, particularly for kanji, results from a mid-fusiform gyrus lesion (Brodmann's Area [BA] 37), whereas pure alexia for kana results from a posterior fusiform/inferior occipital gyri lesion (BA 18/19).

Self-timed Read Termination for Reduced Read Disturbance and Power Consumption in Large-scale Cross-point ReRAM Arrays

We present a self-timed read termination (STRT) to improve read disturbance and reduce power consumption in a large cross-point ReRAM array. Due to the variability of ReRAM cells, a read current is forced to flow through the filament of memory cells for a time after the read decision is made, resulting in unnecessary power consumption and read disturbance. The STRT helps decrease the total read-stress time by approximately 75 % in fully integrated 16-kb cross-point ReRAM arrays. Moreover, the power consumption is decreased by 72.8 % throughout the all LRS 1-Mb ReRAM array when measured in fabricated 16-kb cross-point ReRAM using 350-nm CMOS technology.