Abstract
Subthreshold SRAMs profit various energy-constrained applications. The traditional 6T SRAMs exhibit poor cell stability with voltage scaling. To this end, several 8T to 16T cell designs have been reported to improve the stability. However, they either suffer one of disturbances or consume large bit-area overhead. Furthermore, some cell options have a limited write-ability. This paper presents a novel 8T static RAM for reliable subthreshold operation. The cell employs a fully differential scheme and features cross-point access. An adaptive cell bias for each operating mode eliminates the read disturbance and enlarges the write-ability as well as the half-select stability in a cost-effective small bit-area. The bit-cell also can support efficient bit-interleaving. To verify the SRAM technique, a 32-kbit macro incorporating the proposed cell was implemented with an industrial 180 nm low-power CMOS process. At 0.4 V and room temperature, the proposed cell achieves 3.6× better write-ability and 2.6× higher dummy-read stability compared with the commercialized 8T cell. The 32-kbit SRAM successfully operates down to 0.21 V (~0.27 V lower than transistor threshold voltage). At its lowest operating voltage, the sleep-mode leakage power of entire SRAM is 7.75 nW. Many design results indicate that the proposed SRAM design, which is applicable to an aggressively-scaled process, might be quite useful in realizing cost-effective robust ultra-low voltage SRAMs.
Highlights
Embedded SRAMs are a critical component in memory rich network-on-chip or SoC designs.They are used as buffer memories or caches, and occupy a large portion of area in current system VLSIs.Especially in energy-constrained low-speed biomedical devices and other emerging applications like wireless sensor networks and many wearable devices, subthreshold SRAM designs to extend system operating life-time from limited energy resource have become an ever-important issue
The wordline decoding circuits are located between the two memory blocks
The layout area overhead incurred by two wordline boosters is 0.41% of the macro size, while one negative voltage generator together with 32 column-wise assistline assistline (CAL) drivers consumes 4.75% of the macro area
Summary
Embedded SRAMs are a critical component in memory rich network-on-chip or SoC designs. They are used as buffer memories or caches, and occupy a large portion of area in current system VLSIs. Especially in energy-constrained low-speed biomedical devices and other emerging applications like wireless sensor networks and many wearable devices, subthreshold SRAM designs to extend system operating life-time from limited energy resource have become an ever-important issue. The widely adopted conventional 6T SRAMs exhibit poor cell stability with VDD scaling, severely limiting the minimum operating voltage (VMIN ). To cope with the stability problem at deep-low voltage regime, various SRAM cells composed of different number of transistors have been explored. Some 8T, 9T, 10T, and 12T SRAM cells [11,12,13,14,15,16] employ cross-point
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