Read Disturbance Research Articles

Two-Step Read Scheme in One-Selector and One-RRAM Crossbar-Based Neural Network for Improved Inference Robustness

Introducing a threshold switching selector in a resistive random access memory (RRAM) is essential for implementing a crossbar array that accurately accelerates neuromorphic computations. But, at an expense, a read voltage ( ${V}_{\text {read}}$ ) to be used for inference tasks is inevitably boosted. Therefore, this brief shows the effect of the enlarged ${V}_{\text {read}}$ on the stability of conductance states of the RRAM relevant to the inference robustness. The multiple conductance states of the analog RRAM achieved by a SPICE simulation are stable under consecutive 106 cycles of nominal ${V}_{\text {read}}$ . However, each state of the one selector and one RRAM begins to be disturbed at ~104 cycles due to the boosted ${V}_{\text {read}}$ . More importantly, when a certain state exceeds to the next state due to the accumulated ${V}_{\text {read}}$ stress, a classification accuracy of the neural network is significantly degraded. We, thus, introduce a two-step read scheme that separates the roles of turning on the selector and reading the states. As the selector is turned on rapidly with an additional large pulse, the following ${V}_{\text {read}}$ can be lowered. As a result, the read disturbance is minimized, and the optimized two-step pulse scheme allows 106 MNIST images to be recognized with >95% accuracy in the neural network.

Bit-Level Disturbance-Aware Memory Partitioning for Parallel Data Access for MLC STT-RAM

Spin-transfer torque random access memory (STT-RAM) is one of the most promising emerging nonvolatile memory technologies suitable for substituting traditional memory due to its fascinating features, such as high density and low-leakage power. Multilevel cell (MLC) STT-RAM stores two or more bits in a single cell, which can boost data density. Memory partitioning is an efficient method to overcome the impediment of memory bandwidth restricting the speed of parallel data access. However, when applied to previous memory partitioning methods, MLC STT-RAM is still facing challenges. Since these methods have no respect for the issue of read disturbance, the computation performance is unsatisfactory. In this paper, we propose a bit-level disturbance-aware memory partitioning (BaMP) method for parallel data access on MLC STT-RAM. It can effectively eliminate the conflicts between read operations and check operations, which are caused by the read disturbance of STT-RAM, by scheduling the check operations to different time to avoid conflicts. Moreover, bit-level optimization strategies of check merging and check reducing are integrated into the BaMP flow to exploit the MLC STT-RAM structure. The evaluation results on an open data set show that our BaMP outperforms the state-of-the-art method in terms of bank number, storage overhead, performance, and searching speed.

A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures

We demonstrate a 1-read/1-write two-port (2P) embedded static random access memory macro based on 8T SRAM bitcell with an effective scheme for design of testability. To achieve a smaller macro area, a differential sense amplifier is introduced to read out the data, where the reference voltage for reading 0/1 data is generated by an unselected bitcell array. In addition, we propose a screening test circuit for read disturbance and wordline coupling noise. A 512-kbit 2P SRAM macro using 28-nm high-K/metal gate bulk CMOS technology has been designed, confirming experimentally that the worst minimum operation voltage ( $V_{\text {min}}$ ) can be reproduced by our test circuit. Bit density of 3.16 Mb/mm2 was achieved.

Suppress variations of analog resistive memory for neuromorphic computing by localizing Vo formation

Reducing device to device variations of filamentary analog resistive random access memory (RRAM) is crucial for neuromorphic computing. Larger variations decrease the computing accuracy of the neuromorphic network. One of the main factors for the variations of filamentary RRAM is the random nature of filament formation. This work presents a defect engineering approach using the atomic layer deposition method to localize the oxygen vacancies (Vo) formation uniformly, which results in uniform multi-weak-filaments formed in RRAM devices. The variation of linearity and dynamic ON/OFF ratio in different devices can be suppressed using the proposed method. Besides the variation control in this work, the retention and read disturbance are also optimized by increasing the Vo migration barrier, which are also important for neuromorphic network. The analog RRAM array is demonstrated with good uniformity of analog switching behavior, fast speed, long retention, small read disturbance, which shows tremendous potential in developing large-scale RRAM based neural networks.

A Reliable, Low Power and Nonvolatile MTJ-Based Flip-Flop for Advanced Nanoelectronics

Very large-scale integrated circuit (VLSI) design faces many challenges with today’s nanometer CMOS technology, including leakage current and reliability issues. Magnetic tunnel junction (MTJ) hybrid with CMOS transistors can offer many advantages for future VLSI design such as high performance, low power consumption, easy integration with CMOS and also nonvolatility. However, MTJ-based logic circuits suffer from a reliability challenge that is the read disturbance issue. This paper proposes a new nonvolatile magnetic flip-flop (MFF) that offers a disturbance-free sensing and a low power write operation over the previous MFFs. This magnetic-based logic circuit is based on the previous two-in-one (TIO) MTJ cell that presents the aforementioned attributes. Radiation-induced single event upset, as another reliability challenge, is also taken into consideration for the MFFs and another MFF robust against radiation effects is suggested and evaluated.

(Invited) Voltage-Controlled Magnetic Memory: Recent Progress and Opportunities

We review the recent progress and perspectives of voltage-controlled spintronic memory devices with ultralow dynamic energy dissipation, for applications in high-performance computing. We first discuss progress in the development of magnetic tunnel junctions using voltage-controlled magnetic anisotropy (VCMA) for switching, which exhibit the lowest power consumption MRAM cells to date (single-digit fJ/bit with precessional switching times < 1 ns). The current device and materials-level challenges and opportunities are discussed next, including biasing, VCMA coefficients, reduced read disturbance, and write error rates. We then evaluate array-level performance of this memory considering different use models within the memory hierarchy and different workloads. Recent results, device proposals and material requirements are then discussed for further reduction of write time, error rates, energy, and bit cell size.

Offset-Compensated High-Speed Sense Amplifier for STT-MRAMs

Spin-transfer torque magnetic random access memory (STT-MRAM) has emerged as a promising candidate for next generation computing systems. However, with increasing process variation and decreasing supply voltage, a big design challenge of embedded STT-MRAMs is to guarantee negligible read disturbance and high yield. To deal with the read reliability challenge, an offset compensated, high-speed sense amplifier (OCHS-SA) is proposed, which is based on combining the sensing circuit and latch sense amplifier (SA). The proposed OCHS-SA scheme offers four major advantages including offset compensation, high sensing margin (SM), strong positive feedback, and latching feature with compact area. Simulation results show that the SM is at least 700 mV at VDD = 1 V with a sensing time of 3.5 ns, and it provides the lowest energy consumption/area overhead over compared SAs.

Double MgO-based Perpendicular Magnetic-Tunnel-Junction Spin-valve Structure with a Top Co2Fe6B2 Free Layer using a Single SyAF [Co/Pt]n Layer

A new perpendicular spin-transfer-torque magnetic-tunnel-junction (p-MTJ) spin-valve was developed to achieve a high tunneling magnetoresistance (TMR) ratio. It had a double MgO-based spin-valve structure with a top Co2Fe6B2 free layer and incorporated a single SyAF [Co(0.4 nm)/Pt(0.3 nm)]3 layer and a new buffer layer of Co(0.6)/Pt(0.3)/Co(0.4). It had a TMR ratio of 180% and anisotropy exchange field (Hex) of 3.44 kOe after ex-situ annealing of 350 °C for 30 min under a vacuum below 10−6 torr and a perpendicular magnetic field of 3 tesla, thereby ensuring a memory margin and avoiding read disturbance failures. Its high level of performance was due to the face-center-cubic crystallinity of the MgO tunneling barrier being significantly improved by decreasing its surface roughness (i.e., peak-to-valley length of 1.4 nm).

A Full-Sensing-Margin Dual-Reference Sensing Scheme for Deeply-Scaled STT-RAM

Spin transfer torque-random access memory (STT-RAM) has recently been regarded as one of the most promising non-volatile memory candidates for the next-generation computer architectures. However, the readability issue has become a new obstacle for STT-RAM in deeply-scaled technology nodes, owing to (a) the increasing process-voltage-temperature variations but reduced supply voltage, resulting in low sensing margin (SM); (b) reduced current margin between the read current and the critical write current of magnetic tunnel junction, leading to the high read disturbance (RD). Here, to deal with the readability issue of deeply-scaled STT-RAM, we propose a full-sensing-margin dual-reference sensing (FSM-DRS) scheme via exploiting analog signal processing within the sensing circuit design. The proposed FSM-DRS scheme improves SM significantly but with no increase of RD through: (a) including two reference cells which utilize the same structure of the data cells to provide two reference signals, thus reducing the reference mismatch or regularity problem; and (b) adding an analog signal pre-processing operation between the data and reference signals before decision, doubling SM without increasing RD. In comparison with the typical sensing schemes, our simulation results (under the 40 nm technology node) show that our FSM-DRS scheme has an ~70% enhancement in average SM as well as a $\sim 10\times $ decrease in bit error rate.

A Two-Step Sensing Circuit for the Hysteresis Loop Selector-Based Resistive Non-Volatile Memory Arrays

A high selectivity semiconductor selector is the key component in the ultra-high density and low power 3-D resistive non-volatile memory array. The state-of-art selectors suffer from various issues including low selectivity, high OFF current, and low ON current, which significantly limit the array size and performance. Recently, a hysteresis loop (HL) selector with the high selectivity, moderate ON voltage and large HL window was developed to address the high leakage current issue. In this brief, a two-step sensing scheme is proposed to minimize the read disturbance and sensing power. The proposed two-step sensing circuit could achieve 25-ns fast sensing speed with 3.92-uW low sensing power.

A Novel Read Scheme for Read Disturbance Suppression in 3D NAND Flash Memory

A new read scheme is proposed to suppress read disturbance in unselected strings of three-dimensional (3D) vertical channel flash memories. This new scheme decreases the channel potential difference between select word-line (WL) and adjacent WL by more than 20% and the read disturb due to hot carrier injection in adjacent WL of selected WL is suppressed effectively by about 95%. Meanwhile, boosted channel potential during read operation has been preserved to improve soft programming read disturbance by more than 85% in non-adjacent unselected memory cells, owing to the reduced electric field across tunnel oxide. Compared with the conventional scheme, the proposed scheme leads to a significant improvement in read disturbance characteristics with a shorter read period as well as a simplified waveform of read operation.

A Comparative Study Between Spin-Transfer-Torque and Spin-Hall-Effect Switching Mechanisms in PMTJ Using SPICE

The spin transfer torque magnetoresistive random access memory (STT-MRAM) is the leading candidate for spin-based memories. Nevertheless, the high write energy and read disturbance of the STT-MRAM motivated researchers to find other solutions. The spin Hall effect (SHE)-based MRAM is an alternative for the STT-MRAM, which also provides nonvolatility, zero leakage, and competitive area per bit, but with a lower write current. This paper focuses on a systematic performance analysis of these two proposed memory solutions. The SHE requires an external field to deterministically switch perpendicular magnetic anisotropy magnetic tunnel junction (MTJ). A previous experiment showed that the SHE can switch composite MTJ containing an in-plane layer without any field. In this paper, both traditional and composite MTJ structures are modeled in SPICE, which can reproduce realistic MTJ characteristics with user-defined input parameters. This self-contained model is used to compare the write energy and delay of the STT-MRAM and the SHE magnetoresistive random access memory (SHE-MRAM) for various write schemes including thermal fluctuation. Our simulations show, compared with the STT-MRAM, that the SHE-MRAM improves the write delay and the energy by eight times and seven times, respectively. Based on our extensive analysis incorporating the latest advances in magnetic materials and device technology, we predict that the SHE-MRAM is a feasible low-energy memory solution for future computing systems.

Voltage-Control Spintronics Memory With a Self-Aligned Heavy-Metal Electrode

Voltage-control spintronics memory (VoCSM) is a spintronics-based memory that uses the voltage-control-magnetic-anisotropy (VCMA) effect as a selection method and the spin-Hall effect as a write method, and is a candidate for future nonvolatile main memory because of its advantages such as high density, low energy consumption, and robustness against read disturbance. In this paper, we demonstrate VoCSM with a self-aligned heavy-metal electrode, which is the most desirable in mass production and can expect the lowest critical current ( $I_{C})$ due to its narrow electrode structure. We obtain the value of $I_{C}$ of around $400~\mu \text{A}$ for a magnetic tunnel junction of size $35~{\mathrm{ nm}} \times 245$ nm by using a self-aligned heavy-metal electrode. The value is lowered to one-third that of the conventional VoCSM structure and is comparable with that of spin-transfer torque writing. Moreover, $I_{C}$ decreased due to the VCMA effect and reached $260~\mu \text{A}$ for $\text{V}_{\mathrm {MTJ}} = -0.8$ V. We also found that the diffusion spin current from the lateral region, which is the concern matter of this structure, did not contribute very much to the switching due to the extremely short spin diffusion length of the heavy-metal electrode. It indicates that VoCSM with a self-aligned heavy-metal electrode may lead to the production of high-density and low-energy-consumption memory.

FlowPaP and FlowReR

Handheld devices, such as smartphones and tablets, currently dominate the semiconductor market. The memory access patterns of CPU and IP cores are dramatically different in a handheld device, making the main memory a critical bottleneck of the entire system. As a result, non-volatile memories, such as spin transfer torque magnetoresistive random-access memory (STT-MRAM), are emerging as a replacement for the existing DRAM-based main memory, achieving a wide variety of advantages. However, replacing DRAM with STT-MRAM also results in new design challenges including read disturbance. A simple read-and-restore scheme preserves data integrity under read disturbance, but incurs significant performance and energy overheads. Consequently, by utilizing unique characteristics of mobile applications, we propose FlowPaP, a flow pattern prediction scheme to dynamically predict the write-to-last-read distances for data frames running on a handheld device. FlowPaP identifies and removes unnecessary memory restores originally required for preventing read disturbance, significantly improving energy efficiency and performance for STT-MRAM-based handheld devices. In addition, we propose a flow-based data retention time reduction scheme named FlowReR to further lower energy consumption of STT-MRAM at the expense of reducing its data retention time. FlowReR imposes a second step that marginally trades off the already improved energy efficiency for performance improvements. Experimental results show that, compared to the original read-and-restore scheme, the application of FlowPaP and FlowReR together can simultaneously improve energy efficiency by 34% and performance by 17% for a set of commonly used Android applications.

Distribution and Network of Basal Temporal Language Areas: A Study of the Combination of Electric Cortical Stimulation and Diffusion Tensor Imaging.

The basal temporal language area (BTLA) is considered to have several functions in language processing; however, its brain network is still unknown. This study investigated the distribution and networks of the BTLA using a combination of electric cortical stimulation and diffusion tensor imaging (DTI). 10 patients with intractable focal epilepsy who underwent presurgical evaluation with subdural electrodes were enrolled in this study (language dominant side: 6 patients, language nondominant side: 4 patients). Electric stimulation at 50 Hz was applied to the electrodes during Japanese sentence reading, morphograms (kanji) reading, and syllabograms (kana) reading tasks to identify the BTLA. DTI was used to identify the subcortical fibers originating from the BTLA found by electric stimulation. The BTLA was found in 6 patients who underwent implantation of the subdural electrodes in the dominant hemisphere. The BTLA was located anywhere between 20 mm and 56 mm posterior to the temporal tips. In 3 patients, electric stimulation of some or all areas within the BTLA induced disturbance in reading of kanji words only. DTI detected the inferior longitudinal fasciculus (ILF) in all patients and the uncinate fasciculus (UF) in 1 patient, originating from the BTLA. ILF was detected from both kanji-specific areas and kanji-nonspecific areas. This study indicates that the network of the BTLA is a part of a ventral stream and is mainly composed of the ILF, which acts as a critical structure for lexical retrieval. ILF is also associated with the specific processing of kanji words.

Energy-Aware Adaptive Restore Schemes for MLC STT-RAM Cache

For the sake of higher cell density while achieving near-zero standby power, recent research progress in Magnetic Tunneling Junction (MTJ) devices has leveraged Multi-Level Cell (MLC) configurations of Spin-Transfer Torque Random Access Memory (STT-RAM). However, in orderto mitigate the write disturbance in an MLC strategy, data stored in the soft bit must be restored back immediately after the hard bit switching is completed. Furthermore, as the result of MTJ feature size scaling, the soft bit can be expected to become disturbed by the read sensing current, thus requiring an immediate restore operation to ensure the data reliability. In this paper, we design and analyze a novel Adaptive Restore Scheme for Write Disturbance (ARS-WD) and Read Disturbance (ARS-RD), respectively. ARS-WD alleviates restoration overhead by intentionally overwriting soft bit lines which are less likely to be read. ARS-RD, on the other hand, aggregates the potential writes and restore the soft bit line at the time of its eviction from higher level cache. Both of these two schemes are based on a lightweight forecasting approach for the future read behavior of the cache block. Our experimental results show substantial reduction in soft bit line restore operations, delivering 17.9 percent decrease in overall energy consumption and 9.4 percent increase in IPC, while incurring negligible capacity overhead. Moreover, ARS promotes advantages of MLC to provide a preferable L2 design alternative in terms of energy, area and latency product compared to SLC STT-RAM alternatives.

A read disturbance free differential read SRAM cell for low power and reliable cache in embedded processor

Energy consumption and data stability are vital requirement of cache in embedded processor. SRAM is a natural choice for cache memory owing to their speed and energy efficiency. Noise insertion to the SRAM cell during read is a serious problem which reduces its stability. A read disturbance free differential SRAM cell consisting of seven transistors is proposed here which increases cell stability along with maintaining the most desirable differential read technique for faster read. The read SNM of the proposed cell is 154%, 31% and 58% large than that of the conventional 6T-SRAM cell and 2 other 7T-SRAM cells [5,6] compared here. Various factors such as short circuit current reduction, use of single write access transistor, partial bit line swing etc. reduces the overall energy consumption of the proposed cell by 41% compared to 6T-SRAM cell. The proposed cell is also compared with an eight transistor based read disturbance free SRAM cell. The cell delay of the proposed cell is around 55% lesser than that of the 8T-SRAM cell. Besides CMOS the performance achievement of the proposed 7T-SRAM cell is also validated at miniaturized dimension of 20nm using FinFET based predictive technology model library.

A Survey of Soft-Error Mitigation Techniques for Non-Volatile Memories

Non-volatile memories (NVMs) offer superior density and energy characteristics compared to the conventional memories; however, NVMs suffer from severe reliability issues that can easily eclipse their energy efficiency advantages. In this paper, we survey architectural techniques for improving the soft-error reliability of NVMs, specifically PCM (phase change memory) and STT-RAM (spin transfer torque RAM). We focus on soft-errors, such as resistance drift and write disturbance, in PCM and read disturbance and write failures in STT-RAM. By classifying the research works based on key parameters, we highlight their similarities and distinctions. We hope that this survey will underline the crucial importance of addressing NVM reliability for ensuring their system integration and will be useful for researchers, computer architects and processor designers.

$1\times$ - to $2\times$ -nm perpendicular MTJ Switching at Sub-3-ns Pulses Below $100~\mu$ A for High-Performance Embedded STT-MRAM for Sub-20-nm CMOS

Magnetization switching is confirmed for sub-3-ns pulses below $100~\mu \text{A}$ in perpendicular magnetic tunnel junctions (MTJs) down to 16 nm in diameter. The magnetoresistance ratio exceeded 150%, satisfying requirements for fast read conditions. Using sub-30-nm MTJs, write-error rates of up to an order of −6 (10−6) are demonstrated. Read and write current margins, which are important device designs, are sufficiently large to avoid read disturbances. Moreover, $1\times $ -to- $2\times $ -nm MTJs have sufficient data retention for level-2 or level-3 cache requirements. Furthermore, the MTJ resistance remains stable after 1012 write events. To the best of our knowledge, this is the first demonstration of $1\times $ - to $2\times $ -nm MTJs supporting cache memory along with read–write current margins, fast read operations, low power consumption, sufficient retention, and high endurance.

Write Error Rate and Read Disturbance in Electric-Field-Controlled Magnetic Random-Access Memory

We report experimental results on write error rate and read disturbance as a function of read/write pulse width and amplitude in electric-field-controlled magnetic tunnel junctions (MTJs). Results are shown for 50 nm perpendicular MTJs. We also design and simulate the performance of a 256 kilobit (Kbit) magneto-electric random-access memory (MeRAM) macro in a 28 nm complementary metal-oxide semiconductor (CMOS) process, based on the measured MTJ device data. The results show that existing electric-field-controlled MTJs are capable of delivering write error rates below $10^{{-9}}$ for 10 ns total write and verify time and read disturbance below $10^{{-16}}$ for 2 ns read time in a 256 Kbit MeRAM array.