Abstract
Non-volatile memories (NVMs) offer superior density and energy characteristics compared to the conventional memories; however, NVMs suffer from severe reliability issues that can easily eclipse their energy efficiency advantages. In this paper, we survey architectural techniques for improving the soft-error reliability of NVMs, specifically PCM (phase change memory) and STT-RAM (spin transfer torque RAM). We focus on soft-errors, such as resistance drift and write disturbance, in PCM and read disturbance and write failures in STT-RAM. By classifying the research works based on key parameters, we highlight their similarities and distinctions. We hope that this survey will underline the crucial importance of addressing NVM reliability for ensuring their system integration and will be useful for researchers, computer architects and processor designers.
Highlights
The power budget and memory capacity requirements placed on next-generation computing systems have motivated researchers to explore alternatives of conventional memories, such as DRAM and SRAM
Direct mapping: An N-byte block can be stored in N/2 multi-level cell (MLC) STT-RAM cells, such that even bits are stored in soft-bits and odd bits stored in hard-bits
We presented a survey on techniques for improving the reliability of STT-RAM
Summary
The power budget and memory capacity requirements placed on next-generation computing systems have motivated researchers to explore alternatives of conventional memories, such as DRAM and SRAM. Non-volatile memories, such as PCM and STT-RAM, are widely seen as promising candidates for filling this gap due to their attractive properties, such as high density, near-zero standby power and better-than-flash performance and endurance [1]. The error rate of non-volatile memories (NVMs) can far exceed the correction capability of practical ECCs [4,5], and high-overhead ECC or scrubbing mechanisms will be required to maintain acceptable levels of yield, performance and energy efficiency [3,6]. Device-level techniques have been proposed for addressing these issues, these techniques forgo architecture-level optimization opportunities, and using them in isolation can lead to under-/over-protection with high overheads. Contributions: In this paper, we present a survey of techniques for addressing soft-errors in non-volatile memories.
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