Voltage Ramp Test Research Articles

Real-time study of imaging electron current density on metal filament evolution in SiO2 during in situ TEM

Conductive-bridging random access memory devices are a candidate for artificial synapses for neuromorphic computing. However, there is still an incomplete understanding of the fundamentals of the filament evolution process. In this work, we study the effect of three imaging electron current densities on nanoscale filament dynamics in a model Cu/SiO2/Cu structure during in situ TEM electroforming of the device. We find that the filaments grow from the anode to the cathode in the form of discontinuous precipitates for all the imaging electron current densities. However, increasing the imaging electron current density results in a larger injection of Cu into SiO2. Comparing the results of voltage ramp tests in air, in the TEM vacuum without electron irradiation and, in the TEM vacuum with electron irradiation, we suggest a possible mechanism of filament evolution in vacuum. Specifically, we postulate a vacancy defect generation enabled injection of Cu ions into the dielectric as the mechanism behind filament evolution in vacuum that reconciles differing observations found in the literature.

Diamond-like carbon as gate dielectric for metal–insulator–semiconductor applications

Diamond-like carbon (DLC) has been studied as a dielectric material for future metal–insulator–semiconductor (MIS) technology. In this paper, ultrathin DLC films were deposited on silicon substrates by using the dc magnetron sputtering technique at various deposition voltages. The current–voltage characteristics indicated that the leakage currents of the MIS devices decreased with an increase in deposition voltages, and that a low leakage current ([Formula: see text] A/cm2) was achieved at −2 V bias voltage. The deposition voltage effects on the structures of films were investigated through Raman spectroscopy, which indicated that the sp3 bonding fraction decreased with an increase in the deposition voltage. The ramp-voltage breakdown test revealed high effective breakdown electric field ([Formula: see text]85 MV/cm) for the MIS device with the DLC film deposited at 1100-V deposition. Stress-induced leakage current measurement indicated that the DLC film exhibited excellent reliability.

Design and process related MIM cap reliability improvement

A root cause failure investigation was performed on anomalous (early) MIM capacitor failures on an HBT MMIC process. These failures were only observed on capacitors in the actual MMICs; process control monitor (PCM) capacitors were nominal. Multiple failure analysis techniques were employed to determine the most probable root cause of the early failures. The root cause was determined to be etching of the capacitor dielectric by a chemical used in the MMIC fabrication process, at a step after the capacitors themselves were fully built. It was determined that only CAD layouts with certain features were susceptible to the etching. These features were not present on the PCM capacitors.A design based corrective action was recommended to eliminate the failure mechanism. The effectiveness of the corrective actions was verified with several designed processing experiments. These experiments also demonstrated that the failure rate of the faulty parts increased with the time (even if the parts were not in operation). Finally, the experiments showed that the reliability of a nominal capacitor with a BCB layer on top was better than that of an identical capacitor without the BCB layer. Capacitor reliability modelFor the sake of completeness, the following discussion on ramped voltage TDDB testing of capacitors is included. In this work, ramped voltage data was not used to predict capacitor lifetimes, but it was used to quantitatively compare capacitor reliability by plotting percent cumulative failure versus failure voltage.Normally, destructive ramped voltage testing and the linear field model are employed in order to estimate the lifetime of capacitors.This method has been described in detail elsewhere for intrinsic capacitors (Cramer et al. [1,2,3]). It is generally assumed that defects on or in the capacitor bottom plate or in dielectric itself causes a localized thinning of the dielectric which shortens the intrinsic lifetime of the capacitor, as illustrated in Fig. 2.Extrinsic capacitors require a refinement of the Nominal Thickness Method to the Effective Thickness Method.Typically, plots of percent cumulative failure versus failure voltage will be transformed into plots of percent cumulative failure versus lifetime via the above equations. The shapes of these two plots are nearly identical, only the values on the abscissa are changed from (linear) voltage to (logarithmic) lifetime. Since, in this work, the effort was directed at root cause determination of anomalous failures rather than predictions of expected lifetimes, the linear field model was never employed and the data was always plotted as a function of failure voltage.

Thermal and Electrical Reliability Tests of Air-Gap Through-Silicon Vias

Through-silicon vias (TSVs) with air gaps as the isolators have been developed to reduce the TSV capacitance and to solve the reliability problems associated with thermomechanical stresses. This paper reports the reliability assessment of the air-gap TSVs by measuring the $C$ – $V$ , $I$ – $V$ , and resistance of the TSVs in terms of thermal and electrical stresses with a focus on thermal shock, temperature variations, and voltage ramps. Thermal shock tests are performed to evaluate the insulation capability and the thermomechanical stability of the air gaps. Temperature variations are implemented to investigate the influences of high temperatures on the electrical characteristics of the air-gap TSVs. Voltage ramp tests are carried out, and the time-dependent dielectric breakdown is obtained to evaluate the integrity of the air gaps and the intrinsic barrier capability. The preliminary results show that the air-gap TSVs have good thermal stability, excellent dielectric property, and satisfactory structure and barrier stability.

A Fast $I{-}V$ Screening Measurement for TDDB Assessment of Ultra-Thick Inter-Metal Dielectrics

Semiconductor manufacturing economics necessitate the development of novel and innovative techniques that can replace the traditional time consuming reliability methods, i.e., the constant voltage stress time-dependent dielectric breakdown (CVS-TDDB) tests. We show that positive charge trapping is a dominant process when ultra-thick oxides are stressed through the ramped voltage test. Exploiting the physics behind positive charge generation/trapping at high electric fields, a fast I-V measurement technique is proposed that can be used to effectively distinguish the ultra-thick oxides' intrinsic quality at low electric fields. It will be demonstrated, based on experimental data, that our proposed technique can be a suitable replacement for the CVS-TDDB as a quality screening tool.

A Study On The Dielectric Intrinsic Breakdown Specification

With the introduction of ultra-thin gate oxides (GOXs) and low-k dielectrics into IC manufacturing, some new dielectric failure mechanisms arisen. These changes make the evaluations of dielectric reliability more complex. We propose a new method to accurately define the dielectric intrinsic breakdown specification (Spec) of V-ramp (Voltage ramp) tests. Base on the physical failure process and statistical correlation between V-ramp and TDDB (Time Dependent Dielectric Breakdown) tests, the applicability of our proposed method can be further extended to ultra-thin GOX and low-k dielectrics. A quicker and more accurate judgment on dielectric reliability can be achieved by using our method to better assess dielectric reliability risk.

Progress in DC Testing of Generator Stator Windings: Theoretical Considerations and Laboratory Tests

The aging due to mechanical, thermal, electrical, and environmental stresses of a stator insulation system inherently involves alterations of the material properties that are detrimental to its service operation. When these properties are deteriorated to the point where the material can no longer operate safely under normal stress conditions, it implies that it has reached the end of its useful life. To prevent such forced outages and improve the useful life, condition-based maintenance and diagnostic tests are periodically conducted on stator insulation systems. Among the tests performed to assess the condition of winding insulation, various methods are commonly used, such as partial discharge measurements, hipot, step voltage, and ramped voltage tests (RTs), to name just a few. DC testing, where the current is continuously monitored, whether during a step voltage test, such as the polarization/depolarization test, or during a linearly increasing voltage test, such as the RT, is commonly used in the field in order to assess the quality of stator winding insulating systems of large synchronous rotating machines. Both of these tests are related to the dielectric response of the insulation system. This paper presents theoretical considerations on the dielectric response of the various types of machine winding insulation systems encounter in the field as well as laboratory results on individual bars and coils.

Modeling of the Dielectric Response of a Stator Winding Insulation from a DC Ramp Test

The aging due to mechanical, thermal, electrical and environmental stresses of a stator insulation system inherently involves alterations of the material properties which are detrimental to its service operation. When these properties are deteriorated to the point where the material can no longer operate safely under normal stress conditions, it implies that it has reached the end of its useful life. To prevent such forced outages and even to improve the useful life, condition-based maintenance and diagnostic tests are periodically conducted on stator insulation system. Among the tests performed to assess the condition of winding insulation, various methods are commonly used like partial discharge measurements, hi-pot, step voltage and ramped voltage tests to name just a few. The I-V curve measured during a ramped direct voltage test, as the one obtained in a polarization/depolarization test, includes the contribution of various current components, the capacitive, the absorption, the surface leakage and the bulk conduction currents. These contributions, especially the absorption and the conduction (surface or volume) currents, are not as easy to separate in a ramped voltage test as in a polarization/depolarization test (step voltage test). A modeling of the I-V curve obtained with the ramped voltage test, allowing an easy separation of the leakage current from the absorption and the capacitive currents, is presented in this paper. This modeling is compared with a field measurement on complete stator winding and with a lab measurement on spare coil. The calculated values of the absorption and leakage currents obtained during a ramped direct voltage test are compared with the same components deduced from a polarization/depolarization test.

TDDB Data Generation for Fast Lifetime Projections Based on $V$-Ramp Stress Data

Reduced failure rates required by the industry lead to increased costs and time loss for the chip manufacturer since the efforts for continuous process improvements, qualification, screening, and increased test coverage are generally not paid by the customer. However, related costs can be reduced by improved/accelerated reliability testing methods and an approach to a knowledge-based and application-specific qualification and process monitoring strategy. One example of saving time (and costs) during gate oxide reliability testing is given in this paper, showing that time-dependent dielectric breakdown (TDDB) data for lifetime extrapolation and quality assessment can be generated from linear ramped voltage test (RVT) data with high accuracy. Given the parameter of the RVT stress profile, the concept of equivalence is successfully applied to convert stress time data at each ramp stress level to corresponding accumulated equivalent ages at any one stress level. Taking into account these ages until breakdown, failure probabilities with the model parameters of the stress-life relationship being the only fitting parameters can directly be computed and converted to TDDB failure distributions.

On-Wafer Test Method of Metal-Insulator-Metal Capacitor Life using Time Dependent Dielectric Breakdown

We have developed a novel test method for on-wafer measurement of median time to failure (MTTF) of MIMCAP dielectric under an applied electric field using the concept of Time Dependent Dielectric Breakdown (TDDB). This method requires a small number of samples on wafer, and the tests are relatively quick. The feedback on dielectric quality to production team occurs much sooner than what is possible using conventional TDDB test method. We have also measured MTTF of MIMCAP dielectric using an alternate method called the Ramp Voltage Test, and compared the results with MTTF data from the TDDB method. The results from these two methods were in good agreement. This has enabled us to employ the on-wafer TDDB test method to assess the MIMCAP nitride quality in production and engineering environment.

Impact of failure criteria on the reliability prediction of CMOS devices with ultrathin gate oxides based on voltage ramp stress

The gate oxide reliability prediction based on the soft breakdown (SBD) failure criteria limits the operation voltage of future CMOS technologies. Progressive wear-out observed in ultrathin gate oxides leads to a delayed hard dielectric breakdown and can therefore effectively increase the reliability margin. For quantification of this effect, voltage ramp tests were applied to a large sample size and the results linked to constant voltage stress. Based on area scaling, it will be shown that a significant improvement for n- and p-FET devices is obtained when considering the area independent, uncorrelated progressive wear-out of a localized SBD spot.

Suitability of LN2 impregnated Open-Cell Foam as Electric Insulant for Superconducting Power Equipment

The suitability of an open-cell foam is investigated for the application as electric insulant in superconducting power equipment. The tested foam is made from melamine resin, a thermoset plastic from the aminoplastics group; it is a mechanical very flexible material with excellence compatibility to high and low temperature.The aim of these investigations was to test the aptitude of the liquid nitrogen impregnated open-cell foam with respect to the dielectric properties and the electric strength under different conditions. In this paper the results of permittivity measurements and ramp voltage tests are discussed and an outlook for future applications is given. The tests showed excellence mechanical and thermal characteristics for the application in LN2 vessels. The ACBV of the LN2 impregnated foam was 50 % less than the ACBV of pure LN2.

Effect of oxidation temperature on the quality and reliability of ultrathin gate oxide

In this paper, we have studied the effect of oxidation temperatures on the quality and reliability of the ultrathin oxide. It has been observed that for the same oxide thickness, MOS capacitors exhibit a higher leakage current and lower breakdown voltage when the oxide is grown at a lower temperature. We have correlated this increase in leakage current to the effective electron tunnel mass parameter ( m*) and shown that with reduction in the oxidation temperature, the value of m* reduces, signifying the presence of more defects and an increase in defect-assisted tunneling. Also, voltage ramp tests have been carried out to study the time to breakdown ( t BD) and the shape factor ( β) of the Weibull distribution for these devices. It is found that lowering the oxidation temperature adversely affects both of these parameters.

Determining constant voltage lifetimes for silicon nitride capacitors in a GaAs IC process by a step stress method

The lifetimes of metal–insulator–metal (MIM) capacitors are predicted from voltage step stress data. Capacitor areas of 400, 5625 and 11,250 μm 2 are investigated. The reliability of capacitors subjected to a single or triple DC pulse prior to a breakdown voltage ramp test is predicted at use conditions (5 V). The method of maximum likelihood is employed in this analysis. With this approach, it is found that the effect of capacitor area on the linear field acceleration parameter, γ, is not statistically significant. Also, it is demonstrated that either a single or a triple DC pulse seriously reduces both the MTTF and γ. Further, the triple DC pulse can change the failure distribution from lognormal to Weibull. The data are also fitted to the reciprocal field model and the predicted failure times under use conditions are too large to be physically reasonable, favoring the linear field model. A graphical method is suggested for discerning between the lognormal and Weibull distributions. This study makes extensive use of statistical methods. One of our goals in this paper is to make the reliability community aware of these powerful techniques so that they may become more widespread.

Dielectric Relaxation and Breakdown Detection of Doped Tantalum Oxide High-k Thin Films

While TaO/sub x/, HfO/sub x/, ZrO/sub x/, Hf-doped TaO/sub x/, and Zr-doped TaO/sub x/ thin films are promising high-k gate dielectric candidates, their intrinsic reliability has not yet been investigated. In this paper, the authors examine some fundamental reliability aspects of these high-k films through ramp voltage stress testing. By studying dielectric relaxation and analyzing the transient conductivity, the breakdown mode of the tested high-k film is identified; a sensitive method of breakdown detection in ramped voltage tests is proposed and investigated.

Interlevel Dielectric Failures in Copper/Low-k Structures

Failure modes for inter-level dielectric layers under accelerated test conditions have been evaluated for a range of dielectric diffusion barriers in copper/low-k structures. The dominant failure mechanism for both constant voltage tests and ramped voltage tests was mechanical cracking at the dielectric barrier/low-k interface. Few occurrences of copper diffusion through the bulk ILD were observed. A simple model for the dominant failure mechanism is proposed which hypothesizes crack formation due to the electrostatic force between interdigitated lines followed by copper extrusion into the cracks. The proposed model is consistent with measurements of interfacial adhesion strengths in Cu/low-k stacks.

Dry Etch and Wet Clean Process Characterization of Ultra Low-k (ULK) Material Nanoglass®E

AbstractNANOGLASS®E (NGE) ultra low-k (ULK) dielectric material, with a k-value of ∼2.2, was integrated for 130 nm Cu/ULK interconnect process technology. This work deals with the characterization of reactive ion etching (RIE) and wet chemical processing of this film. Blanket films were characterized for etch rate, surface roughness, k-value change and chemical compatibility. Trench etching and post etch wet clean processes were developed and optimized enabling process integration for single damascene structures. Trench etch processes were evaluated for two etch schemes viz., etching under - photo resist and etching under hardmask. The details of each scheme will be described and advantages observed will be discussed. To evaluate effect of wet clean processes three different formulations were used. After formation of single damascene wafers, metal comb and serpentine structures were measured for metal continuity and bridging. Electrical continuity was achieved for long serpentine structures with 0.18μm/0.18μm line width/spacing. Based on voltage ramp test results the film was found to be sensitive to certain plasma etch conditions.

Pre-breakdown noise in electrically stressed thin SiO 2 layers of MOS devices observed with C-AFM

A conductive atomic force microscope (C-AFM) has been used to analyse the degradation stage (before breakdown, BD) of ultrathin (<6 nm) films of SiO 2 at a nanometer scale. Working on bare gate oxides, the conductive tip of the C-AFM allows the electrical characterization of nanometric areas. Due to the extremely small size of the analysed areas, several features, which can be masked by the current that flows through the overall test structure during standard electrical tests, are observed. In particular, switching between different conduction states and sudden changes of conductivity have been measured during ramped voltage tests, which have been related to the trapping and detrapping of single electronic charges in the defects generated during the electrical stress. This phenomenon, which has been observed during constant voltage stresses in the form of random telegraph signals, has been associated to the pre-breakdown noise measured in poly-gated structures. The C-AFM has also allowed to directly measure the I– V characteristics of the fluctuating spot.

Voltage control characteristics of electrorheological fluid valves

Due to the non-linearity of the electrorheological (ER) characteristics of an ER fluid, controlling the flow through an ER valve is not a straightforward problem. Increasing and subsequently decreasing the electric field applied to the valve to the initial value could give rise to a different pressure drop. In this paper it is shown that these characteristics can easily be obtained using varying or ramp voltage tests. These can give the performance curves of the valve that can be used to control the valve. The characteristic performance curves are compared for valves of different configurations. These valve configurations are shown to give characteristic curves that differ not only in magnitude, but also in the overall shape as well. The points on the curves that dictate the working areas of each valve are identified and plotted to give the opening and closing limits of the valves. A step voltage test is used to confirm the validity of the ramp voltage tests and to highlight time dependent characteristics.

A comprehensive study of indium implantation-induced damage in deep submicrometer nMOSFET: device characterization and damage assessment

The impact of indium channel implantation on the current-voltage characteristics, gate oxide breakdown and hot-carrier reliability of deep submicrometer nMOSFETs is studied in detail. A significantly faster oxide wear-out during ramped-voltage testing and a distinctly enhanced drain current degradation during hot-carrier stressing are observed in devices with implant dose ranging from 1-2 /spl times/ 10/sup 13/ cm/sup -2/. An important generation leakage is also measured in the long-channel MOSFET, although such irregularity is normally not detected in short-channel devices owing to predominant subthreshold current. The loss in device reliability may be attributed to the generation of local amorphous regions in the channel when the implant dose exceeds 10/sup 13/ cm/sup -2/. The limited thermal budget of the subsequent gate oxidation step is generally unable to anneal out these defects, which in turn lead to the formation of local weak spots and strained Si-H bonds in the gate oxide, and dislocation loops in the channel region. This finding raises an important concern on the use of indium implantation in retrograde channel engineering, since implant doses on the order of 10/sup 13/ cm/sup -2/ are often needed for effective suppression of short-channel effects. In order to minimize the loss in device reliability, the damaged lattice would need to be restored using a dedicated thermal annealing cycle prior to gate oxidation. A good correlation between the hot-carrier stress data and the DC current-voltage (DCIV) measurement data is also presented. This makes the DCIV technique a precise, nondestructive monitor for implantation-induced damage in deep submicrometer MOSFET, via a direct measurement of the process-residue interface traps.