Impact of failure criteria on the reliability prediction of CMOS devices with ultrathin gate oxides based on voltage ramp stress

Abstract

The gate oxide reliability prediction based on the soft breakdown (SBD) failure criteria limits the operation voltage of future CMOS technologies. Progressive wear-out observed in ultrathin gate oxides leads to a delayed hard dielectric breakdown and can therefore effectively increase the reliability margin. For quantification of this effect, voltage ramp tests were applied to a large sample size and the results linked to constant voltage stress. Based on area scaling, it will be shown that a significant improvement for n- and p-FET devices is obtained when considering the area independent, uncorrelated progressive wear-out of a localized SBD spot.