Radiation Hardening Techniques Research Articles

Total Dose Effects on Voltage References in 130-nm CMOS Technology

This paper investigates the impact of total ionizing dose (TID) effects on the performance of CMOS voltage reference circuits. Four circuits were designed using a commercial 130-nm CMOS process and without any radiation-hardening technique. Two of the designed circuits generate the output voltage proportional to the bandgap voltage, while the other two generate the output voltage proportional to the MOS threshold voltage. The measured output voltage variation caused by TID was from 1% to 15% for a total dose of up to 500 krad, depending on the circuit topology. The leakage currents induced by radiation in MOS transistors and diodes were the main cause of output voltage variation.

A radiation-hard curvature compensated bandgap voltage reference

In this work a radiation-hardened bandgap voltage reference circuit is presented. The circuit is targeted at precision applications, where trimming can be used to achieve a temperature coefficient smaller than $5~\mbox{ppm}/\mbox{K}$ . Curvature compensation is employed and trimming of the temperature coefficient and the curvature is possible. In order to achieve good performance several techniques were combined. Radiation hardening techniques on layout level were used along with design techniques to improve the robustness against total ionizing dose (TID) and process variations. The radiation hardness requirements were set after preliminary irradiation tests. At the layout level optimized transistors were used while at the topology level, a radiation-hardened trimming scheme was employed to mitigate the impact of leakage currents. Chopping techniques were required to ensure good performance over the process and temperature variations. The bandgap was realized in a standard 180 nm CMOS process and circuit performance was verified using extensive simulations.

Relative logic cell placement for mitigation of charge sharing-induced transients

Design of modern integrated circuits increasingly requires consideration of radiation effects, especially in space and other high-risk environments. With fabrication technologies scaling down both feature sizes and critical charge, a radiation strike in sub-100 nm technologies may affect multiple, physically adjacent nodes. With increasing clock speeds, transient errors in the processing datapath also increase in risk. Modeling single-event multiple-transients (SEMT) for pre-fabrication reliability characterization has become a more common design step, and this work adds to the state-of-the-art by providing a fast and physically-informed characterization flow that captures the effects of single-event multiple-node charge collection through experimentally observed transport mechanisms. Beyond characterization, the study of SEMT vulnerabilities reveals the electronic design automation (EDA) step of standard logic cell placement as a design space for hardening against SEMT-induced errors. This work: (1) analyzes the vulnerability of benchmark circuits against SEMT errors, (2) evaluates the impact of logic on transient propagation, (3) explores EDA placement techniques, and (4) builds an automated design flow for relative placement of cells to mask transient errors, while maintaining compatibility with other radiation hardening techniques. Zero cost to area and marginal impact on timing enable this new cell placement algorithm that masks 30% of SEMT-induced errors.

Influence of Alternate Biasing on TID Effects of Irradiated Mixed-Signal Programmable Arrays

This work investigates the influence of alternate biasing on TID effects in mixed-signal programmable devices. By reducing the time the device is biased when exposed to ionizing radiation, the severity of TID effects is also reduced, due to the increasing in the initial recombination of electron-hole pairs and the radiation induced charge neutralization effect. These effects are investigated considering a switched capacitor filter prototyped in a Field Programmable Analog Array. Eight samples of such device were exposed to gamma radiation while the devices were alternately biased, by repeatedly turning the power on and off, corresponding to different equivalent total biasing times and duty-cycles. Results show increase in radiation tolerance to the alternate biased devices, which is dependent also on the biasing duty-cycle. Considering this behavior, a novel system level radiation hardening technique, based on modular redundancy, associated to an alternate biasing scheme, is also proposed in this paper.

CMOS Rad-Hard Front-End Electronics for Precise Sensors Measurements

This paper reports a single-chip solution for the implementation of radiation-tolerant CMOS front-end electronics (FEE) for applications requiring the acquisition of base-band sensor signals. The FEE has been designed in a $0.35~\mu \text {m}$ CMOS process, and implements a set of parallel conversion channels with high levels of configurability to adapt the resolution, conversion rate, as well as the dynamic input range for the required application. Each conversion channel has been designed with a fully-differential implementation of a configurable-gain instrumentation amplifier, followed by an also configurable dual-slope ADC (DS ADC) up to 16 bits. The ASIC also incorporates precise thermal monitoring, sensor conditioning and error detection functionalities to ensure proper operation in extreme environments. Experimental results confirm that the proposed topologies, in conjunction with the applied radiation-hardening techniques, are reliable enough to be used without loss in the performance in environments with an extended temperature range (between −25 and 125 °C) and a total dose beyond 300 krad.

A Low-Cost, Radiation-Hardened Method for Pipeline Protection in Microprocessors

The aggressive scaling of semiconductor technology has significantly increased the radiation-induced soft-error rate in modern microprocessors. Meanwhile, due to the increasing complexity of modern processor pipelines and the limited error-tolerance capabilities that previous radiation hardening techniques can provide, the existing pipeline protection mechanisms cannot achieve complete protection. This paper proposes a complete and cost-effective pipeline protection mechanism using a self-checking architecture. The radiation-hardened pipeline is achieved by incorporating soft-error- and timing-error-tolerant flip-flop (SETTOFF)-based self-checking cells into the sequential cells of the pipeline. A replay recovery mechanism is also developed at the architectural level to recover the detected errors. The proposed pipeline protection technique is implemented in an OpenRISC microprocessor in a 65-nm technology. A gate-level transient fault-injection and analysis technique is used to evaluate the error-tolerance capability of the proposed hardened pipeline design. The results show that compared with the techniques such as triple modular redundancy, the SETTOFF-based self-checking technique requires over 30% less area and 80% less power overheads. Meanwhile, the error-tolerant and self-checking capabilities of the register allow the proposed pipeline protection technique to provide a noticeably higher level of reliability for different parts of the pipeline compared with the previous pipeline protection techniques.

Soft error interception latch: double node charge sharing SEU tolerant design

As technology scales down, soft errors, because of single event upsets (SEUs) that affect multiple nodes (through multiple node charge sharing), become a serious concern in nanometre technology integrated circuits. Existing radiation hardening techniques provide partial or no immunity when more than one node are affected. A new latch topology is presented that guarantees soft error tolerance when a single node or any arbitrary combination of node pairs is affected by an SEU. The proposed scheme exploits a positive feedback loop which consists of C-elements. Simulation results validate the efficiency of the new design over existing soft error hardening techniques such as BISER, FERST and TPDICE.

Radiation-Hardening Technique for Voltage Reference Circuit in a Standard 130 nm CMOS Technology

A radiation-hardening technique for a CMOS voltage reference circuit is proposed. Its operation principle consists in combining linearly two different NMOS threshold voltages and a Proportional-To-Absolute-Temperature (PTAT) voltage, which allows the compensation of both temperature-induced and radiation-induced discrepancies. This circuit was implemented in a standard 130 nm CMOS technology and designed in two different layouts. Measurements show a good operation with a minimal supply voltage of 2.5 V, a PSRR of 80 dB at 3.3 V. The voltage output shift is around 0.5% under irradiation up to 40 krad(Si). The active area of the circuit is about 0.04 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A PD-SOI based DTI-LOCOS combined cross isolation technique for minimizing TID radiation induced leakage in high density memory

In order to minimize leakage current increase under total ionizing dose (TID) radiation in high density memory circuits, a new isolation technique, combining deep trench isolation (DTI) between the wells, local oxidation of silicon (LOCOS) isolation between the devices within the well, and a P-diffused area in order to limit leakage at the isolation edge is implemented in partly-depleted silicon-on-insulator (PD-SOI) technology. This radiation hardening technique can minimize the layout area by more than 60%, and allows flexible placement of the body contact. Radiation hardened transistors and 256 Kb flash memory chips are designed and fabricated in a 0.6 μm PD-SOI process. Experiments show that no obvious increase in leakage current is observed for single transistors under 1 Mrad(Si) radiation, and that the 256 Kb memory chip still functions well after a TID of 100 krad(Si), with only 50% increase of the active power consumption in read mode.

CMOS IC radiation hardening by design

Design techniques for radiation hardening of integrated circuits in commercial CMOS technologies are presented. Circuits designed with the proposed approaches are more tolerant to both total dose and to single event effects. The main drawback of the techniques for radiation hardening by design is the increase of silicon area, compared with a conventional design.

The Quad-Path Hardening Technique for Switched-Capacitor Circuits

A novel “quad-path” radiation hardening technique is implemented in a switched-capacitor sample/hold amplifier and validated by laser testing. The proposed technique eliminates the signal-range limitations of the original dual-path hardening technique by using both n- and p-type switches with separate dual and complementary signal paths. Single-event effect sample errors are reduced by up to 90%, with minimal speed, power and area penalties.

System-level radiation hardening of fiber-optic sensor for applications in the radiant condition

In order to improve the radiation hardness of fiber-optic sensor for applications in the radiant condition, especially in the condition that the commercial optical components are used, the system-level radiation hardening technique is proposed by taking into account fiber-optic Sagnac interferometer as an example, in this paper. A model for describing the relationship between the random walk coefficient (RWC) of the closed-loop Sagnac interferometer and the optical parameters in optical loop, the radiation-induced attenuation (RIA) in fiber coil is presented. Then, the numerical simulation for the influence of optical parameters on the degradation sensitivity of RWC to the increase of RIA in fiber is implemented. It is found that the tolerance of fiber-optic Sagnac interferometer on the RIA in fiber coil can be improved by using the light source with high output power, making the diameter of fiber coil as large as possible, and utilizing the over-modulation technique. Furthermore, increasing the output power of light source is the most efficient and feasible method. The increase of output power from 0.2mW to 3mW can reduce the degradation of RWC by more than one order of magnitude.

Development, Design and Characterization of a Novel Protocol and Interfaces for the Control and Readout of Front-End Electronics in High Energy Physics Experiments

The new FF-LYNX communication protocol, aiming at the fulfillment of non-homogeneous latency and bandwidth requirements of future High Energy Physics experiments, as well as its implementation into IP Cores available for ASICs development, are described in this paper. The first test-chip implementing FF-LYNX IP-Cores has been designed in the IBM 130 nm CMOS technology, adopting radiation hardening techniques. Transmitter and Receiver interfaces, designed in three different speed options, 4 × F, 8 × F and 16 × F (F=reference clock frequency), as well as different rad-hard FIFOs, constitute the overall architecture of the testchip. A detailed analysis of the area, power consumption and speed has been performed besides the functional characterization, by means of a configurable test-bed. X-ray irradiation tests have been carried out at CERN facilities to verify the Total Ionization Dose hardness of the interfaces, with their full functionality up to 40 Mrad(SiO2).

Radiation hardening techniques for Er/Yb doped optical fibers and amplifiers for space application

We investigated the efficiencies of two different approaches to increase the radiation hardness of optical amplifiers through development of improved rare-earth (RE) doped optical fibers. We demonstrated the efficiency of codoping with Cerium the core of Erbium/Ytterbium doped optical fibers to improve their radiation tolerance. We compared the γ-rays induced degradation of two amplifiers with comparable pre-irradiation characteristics (~19 dB gain for an input power of ~10 dBm): first one is made with the standard core composition whereas the second one is Ce codoped. The radiation tolerance of the Ce-codoped fiber based amplifier is strongly enhanced. Its output gain decrease is limited to ~1.5 dB after a dose of ~900 Gy, independently of the pump power used, which authorizes the use of such fiber-based systems for challenging space missions associated with high total doses. We also showed that the responses of the two amplifiers with or without Ce-codoping can be further improved by another technique: the pre-loading of these fibers with hydrogen. In this case, the gain degradation is limited to 0.4 dB for the amplifier designed with the standard composition fiber whereas 0.2 dB are reported for the one made with Ce-codoped fiber after a cumulated dose of ~900 Gy. The mechanisms explaining the positive influences of these two treatments are discussed.

Total ionizing dose effects on n-channel metal oxide semiconductor transistors with annular-gate and ring-gate layouts

Two-edged-gate, annular-gate and ring-gate N-channel metal oxide semiconductor (NMOS) transistors with two different values of gate oxide thickness (tox) are fabricated in a commercial 0.35 m complementary metal oxide semiconductor (CMOS) process. The tests for the total ionizing dose (TID) effects of the transistors are carried out with a total dose up to 2000 Gy(Si). The results show that the dependence of radiation-induced threshold voltage shift on tox is larger than the power-law tox3. The TID tolerance of the low voltage NMOS (tox=11 nm) is improved from 300 Gy(Si) to over 2000 Gy(Si) by the annular-gate or ring-gate layout. For the high voltage NMOS (tox=26 nm), the annular-gate or ring-gate layout can only mitigate the growth of the off-state leakage current when the total dose is less than 1000 Gy(Si). As radiation hardening techniques, the annular-gate and ring-gate layouts have similar effects, but the annular-gate layout is slightly more effective in terms of the radiation-induced threshold voltage shift and off-state leakage current increase. The test results are theoretically explained by examining and analyzing the experimental data.

宇宙用半導体部品とその耐放射線化技術

宇宙用半導体部品とその耐放射線化技術

On the Radiation Tolerance of SiGe HBT and CMOS-Based Phase Shifters for Space-Based, Phased-Array Antenna Systems

We report the first irradiation results on high-frequency SiGe HBT and CMOS phase shifters for space-based, phased-array antennas used in radar or wireless communication systems. Both phase shifter circuits remain functional with acceptable dc and RF performance up to multi-Mrad proton exposure, and are thus suitable for many orbital applications. In addition, simulation results probing the limits of phase shifter performance in a radiation environment are presented. These results show that both CMOS and SiGe HBT based phase shifters can be used for space-based applications without any specific radiation hardening techniques.

Layout techniques for radiation hardening of standard CMOS active pixel sensors

This article presents a radiation hardened active pixel sensor implemented in a standard 0.35 μm CMOS process. The integrated circuit is composed of a 64 × 64 pixel matrix with a 25 μm pixel pitch and has four different pixel architectures. There are also test structures to permit the characterization of the MOS transistors. The radiation hardening of the circuit is implemented with two layout techniques: enclosed geometry transistors and guard rings. It is shown that, with these techniques, the sensor is able to operate with total ionization doses that surpass 500 krad, which is more than double of the requirement for our application. Also, the techniques do not compromise the optical response of the pixels. To obtain an electrical model of the designed transistors, an EKV MOSFET Model was extracted.

Gate sizing to radiation harden combinational logic

A gate-level radiation hardening technique for cost-effective reduction of the soft error failure rate in combinational logic circuits is described. The key idea is to exploit the asymmetric logical masking probabilities of gates, hardening gates that have the lowest logical masking probability to achieve cost-effective tradeoffs between overhead and soft error failure rate reduction. The asymmetry in the logical masking probabilities at a gate is leveraged by decoupling the physical from the logical (Boolean) aspects of soft error susceptibility of the gate. Gates are hardened to single-event upsets (SEUs) with specified worst case characteristics in increasing order of their logical masking probability, thereby maximizing the reduction in the soft error failure rate for specified overhead costs (area, power, and delay). Gate sizing for radiation hardening uses a novel gate (transistor) sizing technique that is both efficient and accurate. A full set of experimental results for process technologies ranging from 180 to 70 nm demonstrates the cost-effective tradeoffs that can be achieved. On average, the proposed technique has a radiation hardening overhead of 38.3%, 27.1%, and 3.8% in area, power, and delay for worst case SEUs across the four process technologies.

Radiation-hardening techniques of dedicated optical fibres used in plasma diagnostic systems in ITER

This paper addresses the particular need to develop suitable fabrication techniques of glasses to improve the radiation-resistance and extend the lifetime of optical fibres in high radiation background. Two radiation hardening techniques based on hydrogen and fluorine doping of glass have been applied on step index pure silica core optical fibres. The radiation-induced optical absorption and luminescence have been measured in gamma and fission reactor irradiation conditions at SCKCEN, Mol Belgium. The experimental results show that the lowest optical absorption is achieved in the hydrogen-treated fibre sample. However, the luminescence effect remains significant in any type of fibre and cannot be reduced by the investigated radiation hardening techniques.