Layout techniques for radiation hardening of standard CMOS active pixel sensors

Abstract

This article presents a radiation hardened active pixel sensor implemented in a standard 0.35 μm CMOS process. The integrated circuit is composed of a 64 × 64 pixel matrix with a 25 μm pixel pitch and has four different pixel architectures. There are also test structures to permit the characterization of the MOS transistors. The radiation hardening of the circuit is implemented with two layout techniques: enclosed geometry transistors and guard rings. It is shown that, with these techniques, the sensor is able to operate with total ionization doses that surpass 500 krad, which is more than double of the requirement for our application. Also, the techniques do not compromise the optical response of the pixels. To obtain an electrical model of the designed transistors, an EKV MOSFET Model was extracted.