Programmable Gate Array Logic Research Articles

A real-time dynamic range expansion approach of multi-channel sampling system

Dynamic range (DR) is one of the most critical factors for evaluating a signal processing system. It is limited by all electronic components that signal passes through in the circuit, including the amplifier, analog-to-digital converter and etc. Based on the signal acquisition structure of synchronous sampling with multiple conditioning channels, this paper proposed a method to expand the DR of the system. The proposed method involves the iterative algorithm to calculate the gain and offset between different channels, the threshold voltage setting principles of channel switching, and the data combination approach. More importantly, it can easily be applied in programmable logic gate array in the real-time system. On the basis of ensuring system sensitivity, the input voltage range is increased by combining data from different channels, thereby the DR of the system is increased. The experimental results in the sampling board of the vibration and audio signal analyzer show that the method we discussed in this article has a significant effect on DR expansion in the sampling system.

An adaptive laser processing method of multilayer heterogeneous materials by monitoring dynamic spectrum at kHz-MHz level

Laser micro/nano processing exhibits significant advantages in manufacturing capability and performance. However, the properties of ablated materials cannot be sensed and identified during processing is an intractable challenge. In particular, multilayer heterogeneous materials often evolve into excessive residues and damages during laser selective removal. In this study, we developed an adaptive laser processing method that includes material interface adaptive and laser power adaptive for selective removal of multilayer heterogeneous materials by monitoring dynamic spectrum at kHz-MHz level. The mechanism of interface sensing and the threshold of laser selective removal of multilayer materials were investigated. Dual-channel parallel detection mode of the blazed grating with the ultrafast photodetector at the kHz-MHz pulse level has been designed and verified for monitoring adjacent layers synchronously. High-speed signals with a pulse width of 30 ns and a repetition frequency of 0–15 MHz were identified by the Field Programmable Logic Gate Array (FPGA), and pulse-level closed-loop feedback was finished. Patterned selective removal on an FR-4 copper clad laminate (CCL) and flexible printed circuit (FPC) was completed. The method exhibited sensitive signal characteristics, accurately sensed the material interface, and provided a clear criterion for identifying the removal process of multilayer materials by quantitative analysis of signal variation, which provides an innovative scheme for laser intelligent manufacturing of multilayer heterogeneous materials.

Electrically Sensitive Plasmonic Photonic Crystals for Dynamic Upconversion Manipulation

AbstractLocal optical field modulation using plasmonic materials or photonic crystals provides a powerful strategy for enhancing upconversion emission of lanthanide‐doped upconversion nanocrystals (UCNPs). However, it is restricted to static UC enhancement and the corresponding dynamic modulation of UC is yet to be reported, limiting its practical applications in information devices. Here, a dynamic UC modulation system is reported through electric stimulation by integrating UCNPs with electrically sensitive WO3−x plasmonic photonic crystals (PPCs). The tunable emission enhancement of UCNPs varying from five to 26 folds is achieved in WO3−x PPCs/UCNPs hybrids through external electric stimulation within +1.6 and −1.6 V. It stems from the reversible control of the photonic bandgaps and localized surface plasmon resonance of WO3−x PPCs, ascribed to the variation of refractive index and oxygen vacancy of WO3−x, induced by the reversible change of atomic ratio of W5+ to W6+ under different applied voltages. Moreover, the electrically triggered information encryption devices are developed, employing a programmable logic gate array based on WO3−x PPCs/UCNPs with the ability to convert information‐encrypted electrical signals into visible patterns. These observations offer a new attempt to manipulate the UC and will simulate the new applications in the display and optical storage devices.

Method of solving single-event upset for heterogeneous dual field programmable logic gate array for infrared remote sensing camera in orbit

On-orbit reconstruction is a hotspot technology in the field of space infrared remote sensing cameras technology. Since the space infrared remote sensing cameras perform detection work under the space radiation environment, the core part of its image processing unit, which is a static random-access memory type field programmable logic gate array (FPGA), is susceptible to the impact of high-energy particles, especially during single-event upset events. The occurrence of point-like granular noise in remote sensing images will affect the normal imaging detection performance of the system, and even lead to abnormal timing of infrared detectors in severe cases, thereby affecting the normal operation of infrared remote sensing cameras. Aiming at the reliability requirements of the normal operation of space infrared remote sensing cameras in the space radiation environment, we propose a modular architecture of heterogeneous dual FPGA for XilinxVirtex-5 series FPGA, which carries out periodic refresh, reconstruction, and uploading of Virtex-5 series FPGA through antifuse FPGA. The antifuse FPGA periodically refreshes and reconstructs the Virtex-5 series FPGA from a one-time programmable read-only memory and injects the program into the program storage NOR flash device, and periodically refreshes and reconstructs the Virtex-5 series FPGA from NOR flash. This method can refresh and reconstruct the space infrared remote sensing camera in orbit. The in-orbit flight data verification shows that this method can effectively solve the impact of single-particle turnover event and improve the reliability of the infrared remote sensing camera in orbit operation.

SPAD-Based LiDAR With Real-Time Accuracy Calibration and Laser Power Regulation

This brief reports a light detection and range (LiDAR) imager which incorporates an image sensor based on a single-photon avalanche diode (SPAD) with the resolution of 32 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathbf {\times }$ </tex-math></inline-formula> 32, a VCSEL-based laser emission system with the same resolution as image sensor as well as the pixel spacing, and a field programmable logic gate array (FPGA) used to realize the calibration algorithm and control the working time of the LiDAR imager. A gating high-voltage driver circuit drives the image sensor to reduce background noise interference and realize real-time accuracy calibration for the time-to-digital converter (TDC) with the resolution of 200 ps. The common-cathode driver circuit with the narrow pulse, adaptive frequency and power regulation drives different channels of VCSEL based on the time-division multiplexing method to improve the signal-to-noise ratio and reduce power consumption of the LiDAR imager. The LiDAR imager based on the proposed circuit architecture and calibration algorithm can achieve depth imaging up to 10 m revealing a repeatability error of 10 cm at 10 frames/s.

A System-on-Chip Based Hybrid Neuromorphic Compute Node Architecture for Reproducible Hyper-Real-Time Simulations of Spiking Neural Networks.

Despite the great strides neuroscience has made in recent decades, the underlying principles of brain function remain largely unknown. Advancing the field strongly depends on the ability to study large-scale neural networks and perform complex simulations. In this context, simulations in hyper-real-time are of high interest, as they would enable both comprehensive parameter scans and the study of slow processes, such as learning and long-term memory. Not even the fastest supercomputer available today is able to meet the challenge of accurate and reproducible simulation with hyper-real acceleration. The development of novel neuromorphic computer architectures holds out promise, but the high costs and long development cycles for application-specific hardware solutions makes it difficult to keep pace with the rapid developments in neuroscience. However, advances in System-on-Chip (SoC) device technology and tools are now providing interesting new design possibilities for application-specific implementations. Here, we present a novel hybrid software-hardware architecture approach for a neuromorphic compute node intended to work in a multi-node cluster configuration. The node design builds on the Xilinx Zynq-7000 SoC device architecture that combines a powerful programmable logic gate array (FPGA) and a dual-core ARM Cortex-A9 processor extension on a single chip. Our proposed architecture makes use of both and takes advantage of their tight coupling. We show that available SoC device technology can be used to build smaller neuromorphic computing clusters that enable hyper-real-time simulation of networks consisting of tens of thousands of neurons, and are thus capable of meeting the high demands for modeling and simulation in neuroscience.

FPGA-based multi-channel thermocouple temperature measurement system

Aiming at the high and low temperature test requirements of spacecraft before being sent into space, this paper designs and implements a multi-channel thermocouple temperature measurement system based on FPGA.The system adopts thermocouple as temperature sensor, and ADT7310 is used as thermocouple cold junction temperature compensation, which solves the problem of thermocouple cold junction compensation better.The front end adopts AD7193, a 24-bit analog-to-digital converter with low noise, multi-channel and low power consumption, to amplify and A/D convert the signal at measuring junction of thermocouple.The control core is a field programmable logic gate array FPGA, which can better solve the problem of parallel processing of multi-channel temperature signals. At the same time, it uses the transposition method of the thermocouple standard graduation table, the interpolation look-up table algorithm and the cold junction compensation reverse look-up table algorithm, which is effective The temperature measurement accuracy of each channel is improved.The experimental results show that the system can be connected to 24 K-type or T-type thermocouple sensors, the measurement range can reach -200°C∼220°C (73.15K∼493.15K), and the relative error is less than ±0.3%F.S.

FPGA Data Acquisition of Electrical Parameter

A data acquisition system using a Programmable Logic Gate Array (FPGA) and Graphical User Interface (GUI) for visual enhancement designed for Personal Computer is shown. The data acquisition of voltage (V), current (A) and temperature ( ) signals and/or parameters transmitted at high frequency in real time via the system-on-chip (SOC) created on Spartan 6 FPGA. The system-on-chip is achieved by programming the FPGA with a high-speed hardware description language (Verilog) code written for the system, Printed Circuit Board (PCB) was designed for the system and the GUI has been created using a graphical approach utilizing LabVIEW to enable data monitoring on Personal Computer (PC) display. The FPGA requires digital input signals; therefore, an analogue to digital convertor (ADC) is required for the convert sensor data from analogue signal from sensors to digital signals. A voltage level shifter is required to normalise the voltage level standards within the circuity in between the 5V from the ADC converter and the 3.3V voltage requirement for the FPGA. The Spartan 6 FPGA receives data from the analogue sensors via the ADC, the data are wrapped up in packets and transmitted through RS-232 serial port to the PC. The three aforementioned parameters are monitored on the GUI on the PC presented in both numerical and graphical format and all data can be store in a file for backup storage, maintenance or reference purposes.

FPGA Data Acquisition of Electrical Parameter

A data acquisition system using a Programmable Logic Gate Array (FPGA) and Graphical User Interface (GUI) for visual enhancement designed for Personal Computer is shown. The data acquisition of voltage (V), current (A) and temperature ( ) signals and/or parameters transmitted at high frequency in real time via the system-on-chip (SOC) created on Spartan 6 FPGA. The system-on-chip is achieved by programming the FPGA with a high-speed hardware description language (Verilog) code written for the system, Printed Circuit Board (PCB) was designed for the system and the GUI has been created using a graphical approach utilizing LabVIEW to enable data monitoring on Personal Computer (PC) display. The FPGA requires digital input signals; therefore, an analogue to digital convertor (ADC) is required for the convert sensor data from analogue signal from sensors to digital signals. A voltage level shifter is required to normalise the voltage level standards within the circuity in between the 5V from the ADC converter and the 3.3V voltage requirement for the FPGA. The Spartan 6 FPGA receives data from the analogue sensors via the ADC, the data are wrapped up in packets and transmitted through RS-232 serial port to the PC. The three aforementioned parameters are monitored on the GUI on the PC presented in both numerical and graphical format and all data can be store in a file for backup storage, maintenance or reference purposes.

Dynamic upconversion multicolour editing enabled by molecule-assisted opto-electrochemical modulation

Controlling nonlinear optical signals electrically offers many opportunities for technological developments. Lanthanide-activated nanoparticles have recently emerged as leading platforms for nonlinear upconversion of infra-red excitation within nanometric volumes. However, manipulation of upconversion emission is restricted to varying percentages of component materials, nanocrystal structure, and optical pumping conditions. Here, we report temporal modulation of anti-Stokes luminescence by coupling upconversion nanoparticles with an electrochemically responsive molecule. By electrically tailoring orbital energy levels of the molecules anchored on nanoparticle surfaces, we demonstrate reversible control of molecular absorption, resulting in dynamic colour editing of anti-Stokes luminescence at single-particle resolution. Moreover, we show that a programmable logic gate array based on opto-electrochemical modulation can be constructed to convert information-encrypted electrical signals into visible patterns with millisecond photonic readout. These findings offer insights into precise control of anti-Stokes luminescence, while enabling a host of applications from low-threshold infrared logic switches to multichannel, high-fidelity photonic circuits.

Design and Verification of SDRAM Controller Based on FPGA

SDRAM (Synchronous DRAM) has become the memory standard in many digital system designs, because of low price and high read/write speed. In this paper, Based on the analysis of the working principle and characteristics of SDRAM, an SDRAM controller design method is proposed based on field programmable logic gate array FPGA. In order to reduce resource consumption and increase the read and write speed of SDRAM, the performance control of SDRAM is further optimized. We designed SDRAM controller by using Verilog HDL and Altera Quartus II 14.1 software, and simulated about this design with Model Sim-Altera 10.3c software. Then we verified this design by using Cyclone V 5CSEMA5F31C6 FPGA in DE1-SoC development board. The verification results show that the SDRAM is initialized successfully, the input and output data are completely consistent, and it has stable refresh and read and write functions. The SDRAM controller design meets the requirements.

Design of Charge Signal Generator Based on DDS Technology

The charge signal generator was designed by using Field Programmable Logic Gate Array(FPGA), Digital to Analog Conversion (DAC) circuit and charge conversion circuit. The Direct Digital Frequency Synthesis (DDS) was used to realize the frequency modulation, amplitude modulation and phase modulation of the signal. At the same time, the operating principle of the DDS technology and the design ideas of the analog circuit were described in detail. Under the Modelsim software platform, the function simulation of the program was carried out, and the real-time signal was captured and displayed by the SignalTap II logic analyzer. The correctness of the program was proved by the simulation results and the actual waveform. The voltage signal was converted into the charge signal, and joint debugging with the charge converter and the conditioning amplifier. Tests showed that the output waveform can meet the design specification and this proves the validity and reliability of the charge signal generator. The charge signal generator can be used as a standard signal source for the installation and commissioning of loose parts and vibration monitoring system, and it can be used for overhaul inspection of nuclear power stations.

Automatic pattern recognition on electrical signals applied to neutron gamma discrimination

The electrical pattern recognition can be useful in several applications; generally it is used to detect particular events or anomalies in the signal under analysis or to identify precursors, especially in electrophysiology. Each application requires customized algorithms and appropriate signal processing capabilities.In this article we present the pattern recognition applied to neutron and gamma scintillator analysis; the algorithm can be used considering that the incident particles on the detector produce pulses having different shape. The discrimination of particles is performed starting from a reference patterns set. The algorithm has been designed to be efficiently implemented in programmable logic gate array; anyway, considering the broadband of the signals under analysis, the real time implementation needs simply reference set based on a limited number of patterns due to technological constrains. The algorithm can also be applied off line by using a more complex reference pattern sets in order to detect and to classify the pile-up event, or to compress the scintillator data.The proposed pattern recognition algorithm is based on the cross-correlation operator and on the Euclidean distance between the reference pattern and the shape of the signal under analysis. The automatic pattern recognition algorithm and its simulations are reported in the article. In order to verify the performances in the case of scintillator signals, the algorithm has been applied on data acquired by two scintillator systems irradiated by a neutron-γ source at the Frascati Tokamak Upgrade laboratories. The results confirm the suitability of the method and its future usability. With minor changes the systems can be used in different diagnostic fields.

A digital-analog hybrid random number generator based on memristor

Random number generator (RNG) plays an important role in many areas including image encryption, secure communication, radar waveform generation, etc. However, existing analog methods for random number (RN) cannot satisfy the demand of bit rate. In the even worse case, system parameters from analog devices are easily distorted by surroundings, leading to a weak system robustness. As a result, researchers start to turn to digital implementation which is stabler and more efficient than analog counterpart to produce RN. However, digital methods suffer dynamical degradation due to the limited word length effect. Though some remedies, such as increasing computing precision, cascading multiple chaotic systems, pseudo-randomly perturbing the chaotic system, switching multiple chaotic systems, and error compensation method, are proposed, the limitations are even inevitable. Recently, some continuous-time chaotic oscillators combined with digital devices were used to realize RNG, and a novel approach was proposed to solve the dynamical degradation of digital chaotic system by coupling the given digital chaotic map with an analog chaotic system, where the analog chaotic system is used to anti-control the given digital chaotic map. But this method requires a whole continuous-time system realized with analog devices which restrict the performance of the integral system.#br#In this paper, a novel digital-analog hybrid chaotic system with only one analog device is constructed for the production of RN. The chosen analog device is a generalized memristor consisting of a diode bridge and a parallel RC filter.#br#Memristor is the fourth fundamental electronic component which has provoked extensive researches since the successful realization by Stan Williams's group at HP Labs in 2008.#br#The paper is arranged as follows. Firstly, a generalized memristor realized by a memristive circuit is introduced and its basic properties are given. Then the block diagram of the digital-analog hybrid system based on a single memristor feedback is depicted, and the mathematical model of the system is derived from the block diagram. Thirdly, the simple Logistic map is applied to the hybrid model and its dynamic behaviors are simulated and compared with those from the ideal Logistic before a more complex two-way coupled saw tooth map is applied to the same simulation, verifying the effectiveness of the proposed hybrid system. Finally, the complex coupled map is applied to the practical circuit producing RN which passes the NIST test suite smoothly.#br#The hybrid system has the following advantages: firstly, the introduction of the analog memristor is able to overcome the dynamical degradation in a digital system, avoiding the limited word length effect essentially. Secondly, the least analog device alleviates the sensibility to parameters and the restriction on bit rate in analog systems, ensuring that the hybrid system is robust. Thirdly, the system structure can be easily integrated into a relevant system. By designing the circuits of the system, the field programmable logic gate array of digital part can be used to realize chaotic map while the single memristor acts as a feedback to the digital part.#br#The experimental results show that the novel hybrid system is insensitive to the variations of circuit parameters and the produced RN is of great randomness, satisfying the practical applications.

FPGA-Based High Precision Illumination Measurement System: A Prototype Development and Evaluation

The light is a most important natural resource for human to survive .Aiming at the shortcomings of the traditional light intensity measuring instrument ,a kind of high resolution illumination measurement system based on FPGA is designed ,which consists of special BH1750 light sensors and programmable logic gate array (FPGA) . A soft core Nios II is used as controller in the instrument, and BH1750 is put into use to acquire light signal .The testing results show that the design is feasible.

Verilog HDL optimisation design and simulation for modified inversionless Berlerkamp-Massey algorithm and the multiplier over canonical field

Reed-Solomon RS codes have been widely used in a variety of communication systems to protect digital transmission data against errors. This paper adopts the excellent inversionless Berlerkamp-Massey IBM algorithm as solving key equation algorithm for RS 204, 188 and then further modifies it to implement in less hardware resources after comparison with existing other algorithms. After that, we analyse critical path delay of the modified algorithm implemented in hardware and conclude that the multiplier over canonical field dominates a main part of the delay. Therefore, an efficient combinatorial multiplier of 4-input look up table 4-LUT field programmable logic gate array FPGA is designed and then applied to the modified IBM algorithm. Results show that the modified IBM algorithm can be implemented using easier hardware structure, but when the proposed multiplier is applied to the modified IBM algorithm, in comparison with the two multipliers directly represented by a normal basis and matrix form, the speed to solve key equation increases by 10.2% and 18.4%, respectively.

Submicron-sized magnetic tunnel junctions in field programmable logic gate arrays

We experimentally demonstrate the feasibility of reprogrammable logic gate arrays with lateral dimensions down to 10×10μm2. The gates are based on magnetic tunnel junctions which are elliptically patterned by e-beam lithography with sizes down to 200×100nm2. The junctions are realized with different tunneling systems and are investigated magnetically and electrically, where the magnetization reversal of the junctions’ soft magnetic layer is done via currents in conducting lines. The switching currents could be reduced by a factor of about 2 by introducing an additional NiFe layer on top of the lines. Thus it is possible to use these gate arrays within a highly integrated environment.

Design of a Ferroelectric Programmable Logic Gate Array

A programmable logic gate array has been designed utilizing ferroelectric field effect transistors. The design has only a small number of gates, but this could be scaled up to a more useful size. Using FFETs in a logic array gives several advantages. First, it allows real-time programmability to the array to give high speed reconfiguration. It also allows the array to be configured nearly an unlimited number of times, unlike a FLASH FPGA. Finally, the Ferroelectric Programmable Logic Gate Array (FPLGA) can be implemented using a smaller number of transistors because of the inherent logic characteristics of an FFET. The devices were only designed and modeled using Spice models of the circuit, including the FFET. The actual device was not produced. The designs consist of a small array of logic gates. Other gates could easily be produced. They are linked by FFETs that control the logic flow. Timing and logic tables have been produced showing the array can produce a variety of logic combinations at a real time usable speed. This device could be a prototype for a device that could be put into imbedded systems that need the high speed of hardware implementation of logic and the complexity to need to change the logic algorithm. Because of the non-volatile nature of the FFET, it would also be useful in situations that needed to program a logic array once and use it repeatedly after the power has been shut off.

High-speed, cascaded optical logic operations using programmable optical logic gate arrays

Programmable optical logic operations are demonstrated using arrays of nonlatching binary optical switches consisting of vertical-cavity surface-emitting lasers, p-i-n photodetectors and heterojunction bipolar transistors. Individual arrays can perform Boolean optical logic functions at 100 Mb/s using both optical and electrical logic inputs, while the routing and fan-out of the optical logic outputs can be controlled at the gate level. Cascaded optical logic operation is demonstrated using two programmable logic gate arrays.