Abstract
SDRAM (Synchronous DRAM) has become the memory standard in many digital system designs, because of low price and high read/write speed. In this paper, Based on the analysis of the working principle and characteristics of SDRAM, an SDRAM controller design method is proposed based on field programmable logic gate array FPGA. In order to reduce resource consumption and increase the read and write speed of SDRAM, the performance control of SDRAM is further optimized. We designed SDRAM controller by using Verilog HDL and Altera Quartus II 14.1 software, and simulated about this design with Model Sim-Altera 10.3c software. Then we verified this design by using Cyclone V 5CSEMA5F31C6 FPGA in DE1-SoC development board. The verification results show that the SDRAM is initialized successfully, the input and output data are completely consistent, and it has stable refresh and read and write functions. The SDRAM controller design meets the requirements.
Highlights
IntroductionSDRAM is a memory chip to use widely for embedded real-time systems and high-speed data transmission [1] [2]
SDRAM is a memory chip to use widely for embedded real-time systems and high-speed data transmission [1] [2].In the development of computer systems, in order to give full play to the processor's ability to process data at high speed and improve the efficiency of the entire computer system, it is necessary to use cache technology to store input and output data, intermediate calculation results and temporary data exchanged with external memory Final Results
In this paper, Based on the analysis of the working principle and characteristics of SDRAM, an SDRAM controller design method is proposed based on field programmable logic gate array FPGA
Summary
SDRAM is a memory chip to use widely for embedded real-time systems and high-speed data transmission [1] [2]. In the development of computer systems, in order to give full play to the processor's ability to process data at high speed and improve the efficiency of the entire computer system, it is necessary to use cache technology to store input and output data, intermediate calculation results and temporary data exchanged with external memory Final Results. The processor process line is manufactured on the basis of logic technology, using high-speed transistors and multilayer metals to achieve high system performance and operating frequency; and the main memory production line is manufactured on the basis of DRAM technology, using units as much as possible Small area capacitors, low leakage current transistors and multilayer polysilicon interconnects to achieve large capacity, low cost and low refresh intervals. Soates, et al in order to generate a smaller delay in the encoding of the management macro definition module based on the H.264/AVC video decoder, use a four-layer module structure to implement a multi-channel SDRAM controller [11]
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