Verilog HDL optimisation design and simulation for modified inversionless Berlerkamp-Massey algorithm and the multiplier over canonical field

Abstract

Reed-Solomon RS codes have been widely used in a variety of communication systems to protect digital transmission data against errors. This paper adopts the excellent inversionless Berlerkamp-Massey IBM algorithm as solving key equation algorithm for RS 204, 188 and then further modifies it to implement in less hardware resources after comparison with existing other algorithms. After that, we analyse critical path delay of the modified algorithm implemented in hardware and conclude that the multiplier over canonical field dominates a main part of the delay. Therefore, an efficient combinatorial multiplier of 4-input look up table 4-LUT field programmable logic gate array FPGA is designed and then applied to the modified IBM algorithm. Results show that the modified IBM algorithm can be implemented using easier hardware structure, but when the proposed multiplier is applied to the modified IBM algorithm, in comparison with the two multipliers directly represented by a normal basis and matrix form, the speed to solve key equation increases by 10.2% and 18.4%, respectively.