The Acceleration of OPUS Codec Using Processor - FPGA Co-processing

Abstract

Current trends in computing require dedicated chips to speed up computing performances. These dedicated chips or ASICs are designed for specific applications, however, the drawback in this approach is that IC (Integrated Circuits) functionality cannot be changed. In areas where H/W programmability and reconfigurability is required, FPGA is the solution to achieve this. System on Chip (SOC) FPGAs (Field Programmable Gate Arrays) include processor hard blocks connected to fabric through various interconnects. This architecture provides better performance and the ability to run Operating Systems (OS) like Linux <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> that has direct access to programmable FPGA logic. This paper explains how to split the functions of an application code between hard block processor and FPGA fabric logic. OPUS is an open-source audio codec widely used in voice-over-IP (VoiP) applications. The codec execution can be accelerated by moving some of its functions to FPGA logic. One such function of OPUS code is implemented in FPGA logic using High-Level Synthesis (HLS). Shared DDR memory space is used to transfer the data between the processor and FPGA. In this paper, we summarize the reduction in execution time and processor load. The acceleration of OPUS codec allows processing of a greater number of audio channels in the SoC device compared to running the codec entirely on the processor.