Abstract
A data acquisition system using a Programmable Logic Gate Array (FPGA) and Graphical User Interface (GUI) for visual enhancement designed for Personal Computer is shown. The data acquisition of voltage (V), current (A) and temperature ( ) signals and/or parameters transmitted at high frequency in real time via the system-on-chip (SOC) created on Spartan 6 FPGA. The system-on-chip is achieved by programming the FPGA with a high-speed hardware description language (Verilog) code written for the system, Printed Circuit Board (PCB) was designed for the system and the GUI has been created using a graphical approach utilizing LabVIEW to enable data monitoring on Personal Computer (PC) display. The FPGA requires digital input signals; therefore, an analogue to digital convertor (ADC) is required for the convert sensor data from analogue signal from sensors to digital signals. A voltage level shifter is required to normalise the voltage level standards within the circuity in between the 5V from the ADC converter and the 3.3V voltage requirement for the FPGA. The Spartan 6 FPGA receives data from the analogue sensors via the ADC, the data are wrapped up in packets and transmitted through RS-232 serial port to the PC. The three aforementioned parameters are monitored on the GUI on the PC presented in both numerical and graphical format and all data can be store in a file for backup storage, maintenance or reference purposes.
Highlights
XILINX’S Spartan 6 Field Programmable Gate Arrays (FPGA) are reprogrammable integrated blocks consisting of four major FPGA architecture consists of three category of configurable elements blocks and memory block namely the configurable elements are input/output blocks (IOB), core array of configurable logic blocks (CLB), resources for interconnection
It is evident that the substring bit value has been manipulated in a reverse order, the data alteration was achieved within the array; whereby the most significant bit become the least significant bit for the Numeric number bits equivalent as shown on the figure below
It is imperative that user puts several processes in place before being view after acquisition has taken place, as the viewer cannot comprehend the binary values of data from the analogue to digital convertor (ADC)
Summary
XILINX’S Spartan 6 Field Programmable Gate Arrays (FPGA) are reprogrammable integrated blocks consisting of four major FPGA architecture consists of three category of configurable elements blocks and memory block namely the configurable elements are input/output blocks (IOB), core array of configurable logic blocks (CLB), resources for interconnection. The CLB consist of random access memory (RAM) cells to achieve logic function of several variables and stored in the truth table form, the elementary logic gates required for implementation to realize the functions is not essential and a multiplexer is programmed to select one of its inputs. The block operates on three modes namely, FG mode, F mode and FGM mode. There is significant level of user-configurable logic block (CLB) units in the block with interconnections connecting various units such as Multiplexers, flip-flops, memory with on-chip data storage solution (BRAM) without additional external data storage requirement, multiple inputs/outputs. Others includes clock signal oscillator / driver block with phase looped locking (PLL) to provide accurate and stable clock signals for synchronous application and other peripherals such as several switch lights emitting diodes, sensors, seven segments display etc. The codes are normally written in behavioural description modelling, dataflow description modelling (Gate level) and structural modelling approach or even using the Register Transfer Logic (RTL); thereby linking the logic units to obtain complex digital circuits such as finite state machine (FSM), Read Only Memory (ROM), Random Access memory (RAM)
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