Power Cycling Test Research Articles

A High-Resolution In Situ Condition Monitoring Circuit for SiC Gate Turn-Off Thyristor in Grid Applications

Silicon carbide (SiC) gate turn-off (GTO) thyristor is attractive for grid applications due to the excellent performances of high blocking voltage and low ON-resistance. However, the short-circuit reliability issue has become one of the limiting factors. An in situ condition monitoring method for the reliability of SiC GTO is presented in this work. It uses the forward I- V characteristics of anode-gate p-n junction as the reliability degradation precursor of SiC GTO. The monitoring circuit shows a current resolution of 64 μA with the current range of -31~1027 mA. It provides full electrical isolation with 2-kV isolation voltage. Finally, a set of short-circuit power cycling tests are conducted with the monitoring circuit, and the results show that the method proposed in this article can effectively detect the change of I- V characteristics of SiC GTO to predict the degradation of device physical health.

Influence of Lateral Temperature Gradients on the Failure Modes at Power Cycling

In this article, the influence of the insulated gate bipolar transistor (IGBT) chip-near temperature gradient on the failure modes in the power cycling test is investigated with the finite element (FE) simulation and experiment. Two important aspects influencing the temperature gradient are studied: one is the load current pulse duration t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> from the testing aspect; the other is the area ratio between the chip region and direct copper bonding (DCB) top side copper determined by the device package layout. The IGBT chip-near temperature gradient caused by these two factors is first investigated using the FE thermal simulation. It was found that by varying t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> and the area ratio, a significant influence on the temperature gradient of the chip and the average temperature of the solder layer can be achieved, which could lead to different dominating failure modes under the same power cycling test conditions. Furthermore, experiments considering those two factors were designed and performed to verify the inference derived from the simulation. The results show that the failure mode indeed can be shifted because of the changed temperature gradient.

Thermal Characterization of SiC Modules for Variable Frequency Drives

Silicon carbide (SiC) devices can exhibit simultaneously high electro-thermal conductivity and extremely fast switching. To perform optimal designs showing the benefits of SiC in achieving efficiency, size, weight, and cost objectives for electric converters design, it is necessary to establish better models for calculating device losses and an efficient thermal model that can be calibrated to consider the nuances of measurement based thermal equivalent circuits. This work's outputs can be used in a power converter multi-objective optimization process or real-time temperature prediction of drives to improve reliability and maximize performance. The proposed modified loss calculation and thermal model demonstrate the SiC power module's advantages to reduce peak junction temperature and power cycling effects. A detailed power loss calculation and thermal model is developed and tested on a 480 V, 186 A, 150 HP variable frequency drive (VFD) with SiC modules. A comparison between the SiC module and an equivalent rated Si module demonstrates the reduction in power cycling effects, particularly at low-speed operation. Infrared (IR) imaging results and analytical explanations of the phenomenon is provided. Power cycle tests show that higher thermal conductivity is not the only reason contributing to the lower temperature ripple in low-speed operation.

A High-Efficiency IGBT Health Status Assessment Method Based on Data Driven

As a critical device of power electronics, the health status and residual life of the insulated gate bipolar transistor (IGBT), as well as its high-efficiency assessment should be concerned. High-efficiency assessment methods can provide dangerous warning for transportation equipment to avoid catastrophic accidents. This article focuses on the IGBT solder layer failure. We use the finite element simulation combined with the small current junction temperature measurement method to obtain the relationship between the internal structure degradation of the solder layer and the sensitive parameters of the external port under different load conditions. According to the characteristics of port parameters, a data processing method called multiple weight function (WF) network (MWFN) is developed, and the parameter monitoring platform is built. Finally, an IGBT health assessment method based on MWFN is formed. The main advantage of this method is that the best WF is introduced into the neural network to solve the time-consuming problem of updating the high-dimensional weight matrix. In the case study, the active power cycling test was carried out. We obtained the solder layer delamination images by using the 3-D tomography system and the corresponding port parameters by monitoring platform. From the perspective of evaluation results, the proposed method not only performs as well as other mainstream data-driven methods in terms of evaluation accuracy but also has significant advantages in terms of running time.

Prediction of Chip Solder Fatigue in IGBTs

Chip solder degradation is one of the main factors affecting the reliable operation of insulated gate bipolar transistor (IGBT) modules. However, there are still many challenges to get the real lifetime of chip solder. This paper proposes a lifetime consumption prediction method based on chip solder failure. First, the constant high junction temperature fluctuations are applied to IGBT modules for the power cycling tests. The transient thermal resistance is measured to monitor the degradation process of IGBT modules for every 1000 times of aging tests. And the failure degree of chip solder is analyzed by the integral structure function. With the help of scanning acoustic microscope, the failure analysis of aging modules is carried out. The finite element simulation model is established to analyze the transient thermomechanical characteristics of chip solder. Then, the influences of different power cycling conditions on the viscoplastic strain of chip solder are analyzed quantitatively. The average value of the viscoplastic strain increment is obtained by the integral method under large thermal loading. Meanwhile, the method is also applicable to the low thermal loading. Finally, a study case of IGBT modules in a 1.5 MW grid‐side wind power converter is given to demonstrate the validity of the proposed method. © 2020 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC.

Thermal Stress Reduction of Power MOSFET with Dynamic Gate Voltage Control and Circulation Current Injection in Electric Drive Application

While operating an electric drive under different load conditions, power switch devices experience thermal stress which provokes wear-out failures and compromises lifetime. In this paper, a model-based dynamic gate voltage control strategy is proposed to reduce the thermal stress by shaping the profile of conduction losses. Thermal stability criteria are investigated, which limit the gate voltage operating range; thus, current focalization and associated local heat up are avoided. After that, simulations and lifetime estimation are conducted for performance evaluation in two different operation scenarios, which show promising results at high speed operation conditions. Furthermore, a current injection method is applied for low-speed operating conditions to improve the compensation effort. This method is experimentally verified by using a custom proof-of-concept gate driver that supplies an adjustable three-level gate voltage. A three-phase electric drive is prototyped, on which power cycling tests are conducted. The junction temperature is measured and the results confirm the thermal control method.

A Method for the Measurement of the Threshold-Voltage Shift of SiC MOSFETs During Power Cycling Tests

The application of established test routines like power cycling to wide bandgap devices may be not as straightforward as it seems: When power cycling silicon carbide MOSFETs, the original purpose of triggering package related degradations under application-like and accelerated conditions might be influenced by device related changes during the test, such as carrier trapping, which may lead to a shift in the threshold-voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> and, thus, in the operating point. With the aim to track the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> shift during power cycling in order to separate the mechanisms-i.e., to indicate and quantify the different overlapping effects-a novel inline ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> measurement approach is proposed, which can be integrated in existing power cycling test benches with only minor adaptions. First power cycling results with ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> monitoring reveal a shift in the operating point leading to an early failure detection in conjunction with a V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> shift.

Temperature Distribution Evaluation of Single Chip by Multiple Currents V CE (T) Method

With the ever-growing power density in power electronics, the temperature difference between the center and the edge of a chip can easily exceed 40 K, which poses a serious challenge to the reliability of power devices, and evaluation of single-chip temperature distribution will be more significant than classical virtual junction temperature for reliability assessment. In this article, a multicurrent V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CE</sub> ( T) method is proposed to evaluate the single-chip temperature distribution. Unlike the conventional V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CE</sub> ( T) method measuring the saturation voltage at only one small measurement current, this method requires that the voltages are measured at multiple different measurement currents, and then, the temperature distribution is obtained by solving a system of nonlinear equations. To improve the accuracy of the solution, the chip temperature distribution is represented by a mathematical function, which can greatly reduce the unknown parameters in the equations. Two common different shapes (square and rectangle) of the chip are chosen as research objects, this method is successfully applied in the dc power cycling test and verified by the infrared (IR) camera, and the calculation results agreed well with experimental results. Moreover, the possible effects of the introduction of mathematical models on the evaluation results have been discussed. The proposed method extends the conventional V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CE</sub> ( T) method and finds its capability in chip temperature distribution evaluation, which could help investigate fatigue failure from different perspectives.

High-Reliability Wireless Packaging for High-Temperature SiC Power Device Sintered by Novel Organic-Free Nanomaterial

This article presents a wireless packaging design for SiC power device, which displays low induction, good thermal management performance, and excellent high-temperature reliability. A novel organic-free nanomaterial fabricated by ultrafast pulsed laser deposition (PLD) is employed as the bonding material for both die attach and die top. With $t_{\text {on}} =20$ s and $\Delta T_{J} =200$ K, longtime power cycling tests were performed to evaluate the high-temperature reliability of the packaging, and 11 500 cycles were achieved before failure. The Cu ribbon bonded by the nanomaterial eliminated hot spot on the die top and facilitated heat dissipation, which improved thermal management performance of this packaging. Failure analysis and simulation indicate that thermal stress in the interconnection layer is considered as the primary failure mode under high-temperature operation.

Using of bond-wire resistance as aging indicator of semiconductor power modules

This paper investigates the use of wire—bonds contact resistance as indicator to diagnose the health state of power electronics modules. This technique is especially dedicated to monitoring the degradation of the topside interconnection (metallization-wire bonds) when the module is wired with a Kelvin point. One advantage of this indicator is that it can be followed online, without being disturbed by current or voltage, to diagnose the state of health and, possibly, the prognosis of the remaining lifetime of the power module by associating it with a lifetime model. For this purpose, based on power-cycling tests in different conditions, a comparison between this indicator and the one commonly used, i.e. the collector-emitter voltage Vce, shows that the first one is much more sensitive to the degradations, easier to use online and finally should be more suitable for lifetime prognosis.

Effect of short-circuit degradation on the remaining useful lifetime of SiC MOSFETs and its failure analysis

When the SiC MOSFET works in the normal operating conditions, its remaining useful lifetime used to be estimated based on the monitored parameters and the lifetime model derived from accelerated tests. In this case, the degradation caused by abnormal events has not been considered. Therefore, it makes sense to investigate the effect of short-circuit degradation on the remaining useful lifetime of SiC MOSFETs. A different number of repetitive short-circuit events have been introduced into the accelerated power cycling tests to assess the impact. The experimental results indicate a gate degradation with the increasing number of short-circuit repetitions, which leads to higher conduction loss and earlier failure. Further failure analysis is achieved by performing lock-in thermography, scanning electron microscopy, and focused ion beam.

Analysis of the aging mechanism occurring at the bond-wire contact of IGBT power devices during power cycling

This paper focuses on the degradation at the wire bond contact with the metalized pad, and precisely its evolution with the power module aging. In order to induce damage in this particular zone, an accelerated power cycling test is carried out on well-suited devices. The on-state voltage (VCE) is measured during the test as an indicator of the degradation in the wire and metallization. Then, analyses of the interface wire-metallization are done with a numerical microscope and the EBSD (Electron Back-Scattered Diffraction) technique. As a result, an attempt to correlate the evolution of the degradation with the changes in the granular microstructure of the aluminium constituting the wire and metallization is proposed.

Online Thermal Resistance and Reliability Characteristic Monitoring of Power Modules With Ag Sinter Joining and Pb, Pb-Free Solders During Power Cycling Test by SiC TEG Chip

Despite the rapid progression of silicon carbide (SiC) power devices, the thermal characteristic evaluation during power cycling at high temperature (>200 °C) is an issue. In this article, a fast and miniaturized evaluation system with online thermal characteristic measurement function was introduced by an n-doped 4H SiC thermal engineering group (TEG) chip. Online thermal resistance measurement of a power module structure by Ag sinter joining with micron/submicron Ag particles paste in low temperature, low pressure, and cooling system by a thermal interface material bonding was performed. High-temperature reliability was systemically investigated by power cycling tests by switching on / off the power source which is connected to the SiC-TEG chip by Au wires. The total thermal resistance of the power module from the SiC-TEG chip to the cooling system increased from 0.5 to 0.53 K/W with the enhanced power source, and remained almost same after 20 000 power cycling at a swing temperature ΔTj of 150 °C. Furthermore, the SiC-TEG power module structure with the die attached with Pb and Pb-free solders, alongwith the same power source as sinter Ag paste was also measured. The Ag sinter joint possesses the lowest thermal resistance and highest high temperature reliability during power cycling compared with Pb and Pb-free die-attach materials.

Online Accurate Measurement of Steady-Thermal Resistance of SiC MOSFETs for DC Solid-State Power Controller

The steady-state thermal resistance R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> is the key characteristic of SiC MOSFETs, usually used as a failure indicator. Due to the operating mode of SiC MOSFETs in the dc solid-state power controller (dc-SSPC), the junction temperature measurement based on the steady on-state resistance R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dson</sub> of SiC MOSFETs is vital to the accurate online measurement of R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> . The accuracy of a digital oscilloscope is limited by its analog-to-digital converter; therefore, a drain-source voltage clamp circuit (DVCC) needs to be employed for the accurate online R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dson</sub> measurement. However, conventional DVCCs are unsuitable for either the use over a wide range of operating temperature T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">w</sub> or the integration into the dc-SSPC due to their bulk package. Therefore, in this article, a new design of DVCC is proposed that commonly used small-sized components can be easily integrated into the dc-SSPC with a little impact on its overall volume and can accurately perform the online R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dson</sub> measurement. The experimental results verify the high R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dson</sub> measurement accuracy (<; 0.6%) of the proposed DVCC over a wide T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">w</sub> range (25-100 °C), as well as, the accurate online measurement of R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> with an accuracy of 2.3%. The application of the proposed DVCC in the accelerated power cycling tests highlights its potential in the lifetime prediction.

Real-Time Acoustic Emission Monitoring of Wear-Out Failure in SiC Power Electronic Devices During Power Cycling Tests

In the article, acoustic emission (AE) was applied to monitor the wear-out failure in discrete SiC Schottky barrier diodes devices with a Ag sinter die attach to successfully monitor the real-time progress of failure of Al ribbons for the first time. After eliminating background AE noise including the power on-off switch and the ambient noise via a noise filtering process, AE signals were successfully collected for the SiC devices during a power cycling test. Furthermore, AE monitoring was compared to the traditional failure monitoring method using forward voltage. Physics-of-failure analysis was performed, and fatigue cracks, and lift-off in Al ribbons were confirmed as the dominant failure modes for the discrete devices. Specifically, AE counts that correspond to one of the time-domain parameters of AE signals increased with power cycling, thereby corresponding to the observed fatigue cracks in Al ribbons leading to lift-off failure. Additionally, the AE count rate was highly correlated with the crack growth rate. Based on the relationship between an AE count rate and fatigue crack growth rate, the results indicate that AE monitoring can be used to understand the fatigue propagation in Al ribbons (i.e., failure mechanism) and also as an early warning before catastrophic lift-off fracture for power electronic devices.

Sequential V ce(T) Method for the Accurate Measurement of Junction Temperature Distribution Within Press-Pack IGBTs

In this article, a sequential Vce(T) method with separated gate controller is proposed to measure the junction temperature distribution within press-pack insulated gate bipolar transistors (PP IGBTs), which is not possible for traditional temperature measurement methods due to the enclosed structure and external clamping force of the pressure-type package. This proposed method is integrated into a standard dc power cycling test and the steady-state junction temperature distribution is obtained to validate its applicability and effectiveness. The measured junction temperature exhibited a bathtub type distribution within PP IGBTs. The root cause is the deformation of the copper plate, which was also discussed by the finite-element simulation in previous literature. Furthermore, the influence of static characteristic dispersion is excluded by the chip transposition and the thermomechanical coupling effect is confirmed to be the dominant factor of this junction temperature distribution. Finally, the influence of heating current and heating time on junction temperature distribution is also investigated by the proposed method.

Review of Methodologies for Structural Integrity Evaluation of Power Modules

AbstractThis paper reviews the previous research on the methodologies for evaluating structural integrity of wire bonds and die-attachments in power modules. Under power module operation, these parts are subjected to repeated temperature variations which induce repeated thermal stress due to the mismatch in coefficients of thermal expansion (CTE) of the constituent materials. Thus, thermal fatigue phenomena are critical issues for the structural integrity of power modules. In the present paper, we also deal with the evaluation methodologies for thermal fatigue in the temperatures over 200 °C, which are expected operational temperatures for wide bandgap semiconductor power modules. The failure models based on the temperature range ΔT widely used in the power electronics community are critically reviewed from a mechanical engineering viewpoint. Detailed discussion is given concerning the superiority of failure models based on the physical quantities such as the inelastic strain range Δεin, the inelastic strain energy density range ΔWin, and the nonlinear fracture mechanics parameter range ΔT* over the conventional ΔT-based failure models. It is also pointed out that the distributed state concept (DSC) approaches based on the unified constitutive modeling and the unified mechanics theory are promising for evaluating the structural integrity of power modules. Two kinds of test methods, a power cycling test (PCT) and a thermal cycling test (TCT), are discussed in the relation to evaluating the lifetimes of wire-liftoff and die attach cracking.

Active Power Cycling Test Bench for SiC Power MOSFETs—Principles, Design, and Implementation

One way to achieve the best in class reliability is the implementation of a design for reliability methodology into the design process in order to estimate the lifetime of each individual critical component, based on proper reliability models for failure modes. The main drawback of the above-mentioned approach is that it relies on handbook-based reliability models, which usually are only accurate for particular components. This fact causes the necessity to develop a testing procedure for SiC power metal-oxide semiconductor field-effect transistor (MOSFET), to determine its reliability model parameters. Such model could be further implemented in the design for reliability methodology for the high-performance power supply design process. In this article, a cost effective and industrial friendly laboratory setup for active power cycling of SiC power MOSFETs in SOT-227b housing is presented. By this example, various control strategies for accelerated lifetime testing, degradation indicators for wear-out condition monitoring and junction temperature estimation methods are compared on their impact on test results and complexity in either laboratory setup and its maintenance procedure. Technical issues related to the start-up of active power cycling test and failure detection algorithm are discussed. Finally, test results for SiC power MOSFETs subjected to over 63355 power cycles are presented.

Fatigue Crack Networks in the Die-Attach Joint of a Power Semiconductor Module During Power Cycling Testing and Effects of Test Parameters on the Joint Fatigue Life

The fracture mechanisms of a Sn-Ag-Cu lead-free solder joint and the effects of test parameters on power cycling life were investigated. In this study, three levels of average temperature (348, 373 and 398 K), two levels of each of current on-and-off time (2 s/10 s and 5 s/22 s), and three levels of ΔTj (75, 100 and 125 K) were used. Because the thermal expansion of the die-attach material was restrained by Si, equibiaxial tensile and compressive creep deformation occurred during power cycling. This deformation generated fatigue cracks in the central part of the die-attach joint, and the cracks connected to each other, resulting in a fatigue crack network. The fracture occupied 70% or more of the die-attach area and was the dominant factor affecting the joint’s fatigue life. As ΔTj increased, the strain energy density in the central part increased, resulting in a decrease in fatigue life. Although the strain energy density at an average temperature of 398 K decreased by about 10% compared with that at an average temperature of 348 K, the fatigue life decreased to about 40% when the average temperature increased. Continuous dynamic recrystallization occurred during power cycling, leading to fatigue failure in high-energy grain boundaries. Since continuous dynamic recrystallization tended to occur more readily at higher temperatures, the fatigue life decreased with increasing average temperature, even for the same junction temperature range ΔTj. Moreover, the area of equibiaxial tensile and compressive creep deformation in the die-attach material became larger with increasing current on-and-off times. As a result, the fracture area under long current on-and-off time conditions was increased by about 25% in comparison with that under short current on-and-off time conditions.

Power Cycling Capability and Lifetime Estimation of Discrete Silicon Carbide Power Devices

In this work, the three most common lifetime models for power semiconductors i.e. LESIT, CIPS08 and SKiM63 are investigated regarding their applicability for SiC power devices. For this reason, multiple power cycling tests with a large number of devices were performed. The results show that those models can properly reflect the power cycling test results of SiC power semiconductors for higher temperature swings if the model parameter are properly adjusted. However, they show a significant error for lower temperature swings and drastically underestimate the lifetime. This indicates that the inferior power cycling performance of SiC power devices compared to silicon at high temperature swings does not necessarily imply that the service life is affected in the same order of magnitude.