A Method for the Measurement of the Threshold-Voltage Shift of SiC MOSFETs During Power Cycling Tests

Abstract

The application of established test routines like power cycling to wide bandgap devices may be not as straightforward as it seems: When power cycling silicon carbide MOSFETs, the original purpose of triggering package related degradations under application-like and accelerated conditions might be influenced by device related changes during the test, such as carrier trapping, which may lead to a shift in the threshold-voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> and, thus, in the operating point. With the aim to track the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> shift during power cycling in order to separate the mechanisms-i.e., to indicate and quantify the different overlapping effects-a novel inline ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> measurement approach is proposed, which can be integrated in existing power cycling test benches with only minor adaptions. First power cycling results with ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> monitoring reveal a shift in the operating point leading to an early failure detection in conjunction with a V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> shift.