Processing Power Consumption Research Articles

Mussel-Inspired Polymer-Based Composites for Efficient Thermal Management in Dry and Underwater Environments.

To address the escalating power consumption of processors in data centers and the growing emphasis on environmental sustainability, the prospective shift from traditional air-cooling to immersion liquid cooling necessitates multiple functional integrations in polymer-based thermal conductive materials. Here, drawing inspiration from mussels, we showed a copolymer, poly(dimethylsiloxane-co-dopamine methacrylate) (PDMS-DMA), with a variety of reversible molecular interactions and simply combined with liquid metal (EGaIn) can yield a flexible, waterproof, and electrically insulating thermal conductive composite. The obtained PDMS-DMA/EGaIn composites demonstrate a harmonious blend of attributes, including a low modulus (75.8 kPa), high thermal conductivity of 6.9 W m-1 K-1, and rapid room-temperature self-healing capabilities, capable of complete repair within 20 min, even under water. Based on its electrically insulating and water resistance properties, PDMS-DMA/EGaIn emerges as a promising candidate for efficient and stable heat transfer in both air and underwater thermal management. Consequently, this water-resistant polymer-based composite holds significance for application in thermal protective layers for future immersion liquid cooling systems.

RISC-V-Based Evaluation and Strategy Exploration of MRAM Triple-Level Hybrid Cache Systems

Magnetic random access memory (MRAM) is considered one of the most promising memories among nonvolatile memories (NVMs), to replace static random access memory (SRAM) in the computing system to improve its cache performance. In this article, performance evaluation and strategy exploration of three-level hybrid cache systems are conducted under the framework of Reduced InstrucTIon Set Computer-Five (RISC-V) instruction set. First, system-level joint calls of Nvsim, Gem5, McPAT, and other cache emulation architectures are implemented based on the system-level simulator called MAGPIE tool. Based on the performance comparison of spin transfer torque (STT)-MRAM, spin-orbit torque (SOT)-MRAM, and SRAM with varied capacities, a variety of combined CPU three-level hybrid cache architectures are simulated. The performances of the proposed hybrid cache systems and the bus impact of interconnecting are evaluated, with better analysis of the cost of CPU system implementation and interactions among levels of cache. The power consumption of different processors with various instruction sets and cores is also evaluated. It is demonstrated that SOT-MRAM and STT-MRAM show great potential applications as L2 and L3 caches in the RISC-V system. RISC-V shows the potential benefits for future CPU cache. Meanwhile, an adaptive stride prefetching strategy is proposed to address the problem of delay hysteresis and high miss rate of STT-MRAM in the L3 cache. The applicability of this strategy to different storage technologies and the comparison with cutting-edge technologies are also illustrated. Simulation results show that the prefetching strategy can achieve at most 64.12% and 94.55% optimization effects on the miss latency and the miss rate of L3 cache, respectively.

Imitation Learning-Based Performance-Power Trade-Off Uncore Frequency Scaling Policy for Multicore System.

As the importance of uncore components, such as shared cache slices and memory controllers, increases in processor architecture, the percentage of uncore power consumption in the overall power consumption of multicore processors rises significantly. To maximize the power efficiency of a multicore processor system, we investigate the uncore frequency scaling (UFS) policy and propose a novel imitation learning-based uncore frequency control policy. This policy performs online learning based on the DAgger algorithm and converts the annotation cost of online aggregation data into fine-tuning of the expert model. This design optimizes the online learning efficiency and improves the generality of the UFS policy on unseen loads. On the other hand, we shift our policy optimization target to Performance Per Watt (PPW), i.e., the power efficiency of the processor, to avoid saving a percentage of power while losing a larger percentage of performance. The experimental results show that our proposed policy outperforms the current advanced UFS policy in the benchmark test sequence of SPEC CPU2017. Our policy has a maximum improvement of about 10% relative to the performance-first policies. In the unseen processor load, the tuning decision made by our policy after collecting 50 aggregation data can maintain the processor stably near the optimal power efficiency state.

Security and Privacy for Future Healthcare IoT

Computer networks are widely used in today's society, and we utilize the Internet to connect to our home networks. IoT networks are a brand-new category of these networks where we attempt to connect various household equipment and attempt to issue orders from a distance. Hash code or message authentication code (MAC) is used for authentication, and several encryptions and decryption techniques guarantee secrecy. The cost of using traditional cryptographic security techniques in terms of computing resources like memory, processor power, and power consumption is high. There is no proper model/ framework available to address the major security issues of IoT devices. The literature address that still several gaps exist regarding security issues. To secure and protect future healthcare IoT systems, this research will provide a model that combines shallow learning with deep learning.

Fast colored video encryption using block scrambling and multi-key generation

Multimedia information usage is increasing with new technologies such as the Internet of things (IoT), cloud computing, and big data processing. Video is one of the most widely used types of multimedia. Videos are played and transmitted over different networks in many IoT applications. Consequently, securing videos during transmission over various networks is necessary to prevent unauthorized access to the video's content. The existing securing schemes have limitations in terms of high resource consumption and high processing time, which are not liable to IoT devices with limited resources in terms of processor size, memory, time, and power consumption. This paper proposed a new encryption scheme for securing the colored videos. The video frames are extracted, and then, the frame components (red, green, and blue) are separated and padded by zero. Then, every frame component (channel) is split into blocks of different sizes. Then, the scrambled blocks of a component are obtained by applying a zigzag scan, rotating the blocks, and randomly changing the blocks' arrangements. Finally, a secret key produced from a chaotic logistic map is used to encrypt the scrambled frame component. Security analysis and time complexity are used to evaluate the efficiency of the proposed scheme in encrypting the colored videos. The results reveal that the proposed scheme has high-level security and encryption efficiency. Finally, a comparison between the proposed scheme and existing schemes is performed. The results confirmed that the proposed scheme has additional encryption efficiency.

A hardware accelerator for IEEE 802.15.4 Time-Slotted Channel Hopping transceiver

Time-Slotted Channel Hopping (TSCH), an operational mode of the IEEE 802.15.4e standard, imposes a high workload on the embedded processor, mainly due to its precise timing. The limited embedded processor of an edge device cannot satisfy the considerable memory footprint and computational complexity caused by functions that need precise timing in the protocol stack. Moving such duties to hardware seems to be a viable path towards offloading the processor and releasing its resource to be used for running firmware related to the implementation of the upper layers of the protocol stack as well as the application. In this work, a TSCH protocol hardware accelerator is designed and integrated within the digital baseband processor of an IEEE 802.15.4 transceiver. The whole system is implemented targeting the TSMC 65 nm technology. The designed TSCH accelerator has an efficient interface and is totally configurable by the software. It efficiently controls the transceiver, frees up embedded processor cycles, and reduces the interrupt callback to the processor. Therefore, the TSCH hardware accelerator makes it possible to use a cheaper embedded processor or to operate the processor on a lower clock speed which results in lower power consumption. The power analysis of the implemented system shows that, in the minimal setting of the TSCH accelerator, only 0.1% is added to the power consumption of the digital baseband processor. The power overhead increases to 5.6% for supporting three parallel slotframes which is a widely used TSCH setting in multi-hop networks. In return, the embedded processor is relaxed of processing TSCH timing related interrupts that are required for software-based TSCH implementation.

A High-Performance and Scalable NVMe Controller Featuring Hardware Acceleration

Nonvolatile memory express (NVMe) is a high-performance and scalable PCI express (PCIe)-based interface for the host software communicating with NVMs, including NAND Flash and the storage class memories (SCMs). NVMe solid-state drives (SSDs) have been deployed in cloud platforms and data-centers for a variety of I/O intensive applications due to their performance benefits compared to SATA/SAS SSDs. Considering the design flexibility, firmware-based NVMe controllers are typically used in Flash-based NVMe SSDs but may occupy a significant portion of processor resources and power consumption to achieve high performance. Moreover, the firmware component can be a critical performance bottleneck for SCMs that are an order-of-magnitude faster than Flash. To address these challenges, hardware-accelerated NVMe controllers have emerged in both industry and academia. The commercial hardware controllers are confidential, whereas current academic studies still spare much room for architecture innovations. In this article, we propose an opensource ultralow-latency and high-throughput NVMe controller with a highly parallel, pipelined, and scalable architecture that accommodates one admin controller and multiple fully hardware-automated I/O controllers. We perform extensive empirical performance evaluations concerning the NVMe I/O size, queue depth, queue number, read-to-write ratio, and access pattern. The maximum read/write bandwidth can achieve 7.0 GB/s, accounting for 89&#x0025; of the PCIe bandwidth. The 4-KB-sized read/write throughput can attain 1.7 million I/O operations per second (MIOPS), whereas the average latency is merely 2.4 <inline-formula> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula>/3.2 <inline-formula> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula>. Compared to state-of-the-art NVMe controllers in academia, the 4-KB-sized read/write bandwidth of our controller reaches <inline-formula> <tex-math notation="LaTeX">$2.2 \times /2.3\times $ </tex-math></inline-formula> as high and the latency is <inline-formula> <tex-math notation="LaTeX">$5.1 \times /4.9\times $ </tex-math></inline-formula> lower.

TESTING AMD RYZEN MICROPROCESSOR AND ITS ENERGY EFFICIENCY

In this paper, we show a case study of Ryzen processor energy efficiency using SPECjbb2015 as the workload. We analyze it in comparison to Phenom II, a CPU of previous generation from the same manufacturer AMD. In terms of maxi-mum transaction throughput, Ryzen performs 218% of Phenom. With the response time constraint, the relative performance of Ryzen is 288%. In the energy efficiency, Ryzen achieves 309% (at maximum throughput) and 389% (with response time constraints) of Phenom. Dynamic frequency scaling (DFS) is effective for reducing the power consumption of both processors, but the load levels at which DFS is most effective are quite different.

Tight Lower bound on power consumption for scheduling real-time periodic tasks in core-level DVFS systems

Dynamic voltage and frequency scaling (DVFS) is a widely used solution to reduce power consumption. Modern multi-core architectures support core-level DVFS, where each core has its own power supply and can change its frequency independently from other cores. This paper aims at optimizing power consumption of multi-core processors while ensuring deadline constraints of real-time periodic tasks. From theoretical aspects, we prove a tight lower bound of power consumption for executing real-time tasks, which indicates to what extent scheduling algorithms can approach. From practical aspects, we propose a Power Scaling Algorithm (PSA) to assign real-time periodic tasks to a power efficient platform. PSA not only determines the optimal frequencies for each core, but also provides the appropriate number of active cores, which can skip the local optimum and achieve the global minimum. This lower power bound is validated by several extensive experiments.

Energy Efficient UAV-Based Service Offloading Over Cloud-Fog Architectures

Unmanned Aerial Vehicles (UAVs) are poised to play a central role in revolutionizing future services offered by the envisioned smart cities, thanks to their agility, flexibility, and cost-efficiency. UAVs are being widely deployed in different verticals including surveillance, search and rescue missions, delivery of items, and as an infrastructure for aerial communications in future wireless networks. UAVs can be used to survey target locations, collect raw data from the ground (i.e., video streams), generate computing task(s) and offload it to the available servers for processing. In this work, we formulate a multi-objective optimization framework for both the network resource allocation and the UAV trajectory planning problem using Mixed Integer Linear Programming (MILP) optimization model. In consideration of the different stake holders that may exist in a Cloud-Fog environment, we minimize the sum of a weighted objective function, which allows network operators to tune the weights to emphasize/de-emphasize different cost functions such as the end-to-end network power consumption (EENPC), processing power consumption (PPC), UAV&#x2019;s total flight distance (UAVTFD), and UAV&#x2019;s total power consumption (UAVTPC). Our optimization models and results enable the optimum offloading decisions to be made under different constraints relating to EENPC, PPC, UAVTFD and UAVTPC which we explore in detail. For example, when the UAV&#x2019;s propulsion efficiency (UPE) is at its worst (10% considered), offloading via the macro base station is the best choice and a maximum power saving of 34% can be achieved. Extensive studies on the UAV&#x2019;s coverage path planning (CPP) and computation offloading have been conducted, but none has tackled the issue in a practical Cloud-Fog architecture in which all the elements of the access, metro and core layers are considered when evaluating the service offloading in a distributed architecture like the Cloud-Fog.

Design Space Exploration of Single-Lane OFDM-Based Serial Links for High-Speed Wireline Communications

The 4-level pulse-amplitude modulation (PAM-4) with an analog-digital converter (ADC)-based receiver (RX) has become the most commonly employed modulation for ultra-high-speed serial links with the data rate above 100 Gb/s. To support the data rate of 200 Gb/s, orthogonal frequency division multiplexing (OFDM) has been studied recently as one of the possible modulation schemes in the next-generation serial links. The OFDM can feature high bandwidth efficiency without increasing the equalization complexity, leading to a reduced maximum signal amplitude attenuation and lower required DAC/ADC conversion rates given sufficient DAC/ADC resolutions such that the BER is not primarily limited by the data converters&#x2019; resolution. This paper presents system-level modeling results of OFDM-based wireline serial links, with a particular emphasis on the impacts of the fast Fourier transform (FFT) processor&#x2019;s tap count on the serial link performance. The relationship among the cyclic prefix (CP), FFT tap count, and the link bit-error-rate (BER) are thoroughly explained. The analysis explains that the power consumption of a partially-serial FFT processor improves with a larger kernel FFT size, and simulation results show that the BER performance improves with the FFT size where an optimal CP length exists given the FFT size.

Advances in parallel and distributed computing and its applications

Advances in parallel and distributed computing and its applications

Viability of Cryogenic Cooling to Reduce Processor Power Consumption

Abstract Through the application of cryogenic cooling via liquid nitrogen (LN2), the power consumption of a CPU was substantially reduced. Using a digitally controlled solenoid valve and an additively manufactured cold plate, the manual process of LN2 cooling was automated for precise control of cold plate temperature. The power consumption and frequency relationship of the processor were established across three different thermal solutions to demonstrate the effect of temperature on this relationship. It was found that power consumption of the processor decreased at lower temperatures due to a reduction in current leakage and the core voltage necessary for stable operation. This culminated in a reduction of up to 10.7% in processor power consumption for the automated solution and 21.5% for the manual LN2 solution when compared to the air-cooled baseline. Due to the binary nature of the solenoid valve used, flow rate was tuned via an in-line needle valve to increase thermal stability. It was found that for lower flow rates, approximately 5.0 g/s, temperatures oscillated within a range of ±11.5 °C while for higher flow rates of 10–12 g/s, generated amplitudes are as small as ±3.5 °C. Additionally, several tests measured the rate of LN2 consumption and found that the automated solution used 230%–280% more coolant than the manual thermal solution, implying there is room for improvement in the cold plate geometry, LN2 vapor exhaust design, and coolant delivery optimization.

A Heterogeneous Hardware Accelerator for Image Classification in Embedded Systems

Convolutional neural networks (CNN) have been extensively employed for image classification due to their high accuracy. However, inference is a computationally-intensive process that often requires hardware acceleration to operate in real time. For mobile devices, the power consumption of graphics processors (GPUs) is frequently prohibitive, and field-programmable gate arrays (FPGA) become a solution to perform inference at high speed. Although previous works have implemented CNN inference on FPGAs, their high utilization of on-chip memory and arithmetic resources complicate their application on resource-constrained edge devices. In this paper, we present a scalable, low power, low resource-utilization accelerator architecture for inference on the MobileNet V2 CNN. The architecture uses a heterogeneous system with an embedded processor as the main controller, external memory to store network data, and dedicated hardware implemented on reconfigurable logic with a scalable number of processing elements (PE). Implemented on a XCZU7EV FPGA running at 200 MHz and using four PEs, the accelerator infers with 87% top-5 accuracy and processes an image of pixels in 220 ms. It consumes 7.35 W of power and uses less than 30% of the logic and arithmetic resources used by other MobileNet FPGA accelerators.

Thermal design power and vectorized instructions behavior

AbstractVectorized instructions were introduced to improve the performance of applications. However, they come at the cost of an increase in the power consumption. As a consequence, processors are designed to limit their frequency when such instructions are used in order to respect the thermal design power limit. In this paper, we study and compare the impact of thermal design power and Simple Instruction Multiple Data (SIMD) instructions on performance, power and energy consumption of processors and memory. The study is performed on three different architectures providing different characteristics and four applications with different profiles (including one application with different phases, each phase having a different profile). The study shows that, because of processor frequency, performance and power consumption are strongly related to thermal design power. It also shows that AVX512 has unexpected behavior regarding processor power consumption, while DRAM power consumption is impacted by SIMD instructions because of the generated memory throughput. Finally, this paper tackles the impact of turboboost which shows equivalent to better performance for all the studied cases while not always decreasing energy consumption.

Static power model for CMOS and FPGA circuits

In Ultra-Low-Power (ULP) applications, power consumption is a key parameter for process independent architectural level design decisions. Traditionally, time-consuming Spice simulations are used to measure the static power consumption. Herein, a technology-independent static power estimation model is presented, which can estimate static power with reasonable accuracy in much less time. It is shown that active area only is not a good indicator for static power consumption, hence in this model, the effects of transistor sizing, transistor stacking, gate boosting and voltage change are considered. The procedure to apply this model to processors and FPGAs is demonstrated. Across different process technologies, compared to traditional spice simulation, this model can estimate the static power consumption of processor with an error of 1%–4%, while static power consumption of an FPGA system with an error of 1%–15%.

Emerging trends in the developments of low power design technique

In this paper is introduced a low power design technique for developing more reliable, functional, and more cost-effective handheld cellular telephones, portable computers, and peripherals. The portability requirements of handheld computers and other portable devices have placed tremendous pressure on electronic equipment designers, who need to deal with restrictions in the size of electronic units and power consumption. Even though battery technology is continuously improving, including reduced power consumption of processors and displays, extensive and continuous use of network services aggravates these issues. Now the onus is on the research and industrial communities to extend battery life and reduce weight. Equally, research on new techniques and technologies continues, to carefully manage energy consumption in mobile devices, while still providing continuous and fast connections to services and applications. This paper also discusses the novel trends in the developments and advancements in the area of low power Very Large Scale Integration (VLSI) design, dynamic power dissipation static power loss in Complementary Metal Oxide Semiconductor (CMOS), and advanced low power technique. Though low power as a well-established domain that undergone lots of developments from transistor sizing, process shrinkage, voltage scaling, clock gating, etc., to adiabatic logic are elaborated.

Evolution-Based Real-Time Job Scheduling for Co-Optimizing Processor and Memory Power Savings

With the recent advances in battery-based mobile computing technologies, power-saving techniques in real-time embedded devices are becoming increasingly important. This paper presents a novel job scheduling policy for real-time systems, which aims at minimizing the power consumption of processor and memory without missing the deadline constraints of real-time jobs. To do so, we formulate the power saving techniques of processor voltage/frequency scaling and memory job placement as a unified measure, and show that it is a complex search problem that has the exponential time complexity. Thus, an efficient heuristic based on evolutionary computation is performed to cut down the huge searching space and find a reasonable schedule within the feasible time budget. To evaluate the proposed scheduling policy, we conduct experiments under various workload conditions. Our experimental results show that the proposed policy significantly reduces the energy consumption of real-time systems. Specifically, the average reduction in the energy consumption is 41.7% without deadline misses.

Design and Analysis of Low Power SRAM using CMOS Technology

The power consumption in commercial processors and application specific integrated circuits increases with decreasing technology nodes. Power saving techniques have become a first class design point for current and future VLSI systems. These systems employ large on-chip SRAM memories. Reducing memory leakage power while maintaining data integrity is a key criterion for modern day systems. Unfortunately, state of the art techniques like power-gating can only be applied to logic as these would destroy the contents of the memory if applied to a SRAM system. Fortunately, previous works have noted large temporal and spatial locality for data patterns in commerical processors as well as application specific ICs that work on images, audio and video data. This paper presents a novel column based Energy Compression technique that saves SRAM power by selectively turning off cells based on a data pattern. This technique is applied to study the power savings in application specific inegrated circuit SRAM memories and can also be applied for commercial processors. The paper also evaluates the effects of processing images before storage and data cluster patterns for optimizing power savings..

Design of Low-Power SoC for Wearable Healthcare Device

In wearable devices, power consumption is a serious issue since wearable devices must maintain the power-on state at any time. In healthcare system, a variety of signal processing operations occupy a large portion of overall workload because it has periodic and heavy computational workloads. In this paper, we propose a low-power System on Chip (SoC) architecture for wearable healthcare devices. In order to reduce power consumption of processor, we design a hardware accelerator that handles signal processing and provides computation offloading. Furthermore, to minimize the area and maximize the performance of the accelerator, we optimize the operation bit-width by analyzing the frequency response. The low-power healthcare SoC was fabricated with 0.11[Formula: see text][Formula: see text]m CMOS process. Finally, we measured the power consumption of our chip and verified the applicability of the digital filter accelerator, which reduces the energy consumption for embedded processor.