Processing Power Consumption Research Articles

Real-Time RFI Processor for Future Spaceborne Microwave Radiometers

Anthropogenic radio frequency interference (RFI) within microwave radiometer bands is a serious problem in remote sensing. The problem is ever-increasing and thus, future spaceborne microwave radiometers will require efficient methods to mitigate the effects of RFI. In this paper, we present a solution: an RFI processor to detect and blank the RFI in real time. The processor was designed to be compatible with the 18.7-GHz channel of the Microwave Imager Instrument onboard the European MetOp Second Generation satellite system. The RFI processor developed here applies the following complementary detection algorithms: 1) anomalous amplitude detection; 2) kurtosis; and 3) two different cross-frequency algorithms. In the processing, the data are divided into subsamples with fine temporal and frequency resolution. The RFI processor detects and filters out RFI with this fine resolution in real time and then integrates the clean (noncontaminated) subsamples over time and frequency. Thus, a cleaned version of the radiometer data can be downlinked at a traditional low data rate. The processing is implemented in a reprogrammable field programmable gate array with high processing capacity, which provides high flexibility. The processing bandwidth that is applied is 200 MHz (+ 25-MHz transition bands on both sides). The detection limits of the system vary between various kinds of RFI but are in line with simulations. The power consumption of the RFI processor is ∼12 W (at room temperature), and its mass is ∼1.1 kg.

English

English

Energy-Efficient Control of Mobile Processors Based on Long Short-Term Memory

Smartphones that are equipped with high-clock frequency and multi-core processors are being commercially released to provide various services. As the number of cores and the clock speed of a mobile processor increases, its power consumption also increases, and several software approaches to reducing power consumption have been studied. Existing techniques estimate processor usage by measuring the processor usage at a previous time. However, these techniques often waste energy because they assign frequencies above the usage required to prevent degraded user responsiveness. Therefore, this paper proposes a machine learning method to predict the usage that the processor currently requires to prevent performance degradation while reducing power consumption. The proposed method is implemented through a processor power management system based on Long Short-Term Memory (LSTM). This system learns processor usage patterns in a variety of situations and predicts the processor usage required for the current situation. The number of computations required by the LSTM-based technique is analyzed according to the number of neurons and layers, and the computational load is then compared to an existing technique. Furthermore, a benchmarking tool that reflects the characteristics of mobile applications is used to test the performance of the proposed system, which is shown to reduce the power consumption of mobile processors by a maximum of 19% compared to the existing Android processor power management system.

Low-Power Scalable 3-D Face Frontalization Processor for CNN-Based Face Recognition in Mobile Devices

A low-power scalable 3-D face frontalization processor is proposed for accurate face recognition in mobile devices. In spite of recent improvement in face recognition accuracy mainly from convolutional neural networks (CNNs), their performance is limited to face images with frontal view. For face recognition with human-level accuracy in real-life environment, in which most of the face images are captured from arbitrary angles, 3-D face frontalization is essential as a preprocessing stage for CNN-based face recognition algorithms. The proposed face frontalization processor shows scalability in two aspects: image resolution and accuracy. For low-power consumption and scalability, the processor proposes three features: 1) scalable processing element (PE) architecture with workload adaptation; 2) accuracy scalable regression weight quantization to reduce the external memory access (EMA) down to 81.3%; and 3) pipelined memory-level zero-skipping to further reduce the EMA by 98.4% without any latency overhead. From the proposed EMA reduction features, the EMA is reduced by 99.7% with little accuracy degradation in face frontalization results. The proposed face frontalization processor is implemented in 65-nm CMOS process, and it shows 4.73 frames/s) throughput. Moreover, power consumption of the implemented face frontalization processor is 0.53 mW, which is suitable for applications on mobile devices.

An Online Learning Methodology for Performance Modeling of Graphics Processors

Approximately 18 percent of the 3.2 million smartphone applications rely on integrated graphics processing units (GPUs) to achieve competitive performance. Graphics performance, typically measured in frames per second, is a strong function of the GPU frequency, which in turn has a significant impact on mobile processor power consumption. Consequently, dynamic power management algorithms have to assess the performance sensitivity to the frequency accurately to choose the operating frequency of the GPU effectively. Since the impact of GPU frequency on performance varies rapidly over time, there is a need for online performance models that can adapt to varying workloads. This paper presents a light-weight adaptive runtime performance model that predicts the frame processing time of graphics workloads at runtime without apriori characterization. We employ this model to estimate the frame time sensitivity to the GPU frequency, i.e., the partial derivative of the frame time with respect to the GPU frequency. The proposed model does not rely on any parameter learned offline. Our experiments on commercial platforms with common GPU benchmarks show that the mean absolute percentage error in frame time and frame time sensitivity prediction are 4.2 and 6.7 percent, respectively.

CNFET-Based High Throughput SIMD Architecture

Carbon nanotube field effect transistor (CNFET), using the carbon nanotubes (CNTs) as the material for conducting, is a promising alternative of CMOS technology to overcome the “power wall” issue. Recently, a microprocessor solely based on CNFETs was fabricated and demonstrated, which is a big step forward to the industrial practice. However, CNFETs are inherently subject to much larger process variation or manufacturing defects; thereby it may cause significant design cost to build high performance processors. This is exacerbated in the large register file (RF) architectures widely used in single instruction multiple data (SIMD) architectures, e.g., general public utilities style processors, where the number of critical paths are multiplied by the SIMD width and thread count. In this paper, we seek cost-effective approaches to address the issues by judiciously exploiting the strong asymmetric spatial correlation in the variation unique to the CNFET fabrication process. This paper presents a microarchitectural model to characterize CNFET delay variation and malfunction, under which we show that the RF organizations coupled with the architectural schemes are critical to the performance and power consumption of the SIMD processor. Therefore, we propose several architectural techniques to mitigate the performance degradation and the impact of CNT metallization, leveraging the distinctive CNFET characteristics and the unique features in the SIMD processors. Experimental results verify the effectiveness of the proposed techniques and demonstrate the great opportunity offered by this new device technology.

Analysis and Implementation of Hybrid FIR Architecture in Speech Processor

Hearing aid is an electronic gadget precisely used into the internal ear which reestablishes halfway hearing to smooth hearing. The discourse processor of CI parts the sound-related sign into groups of various frequencies and changes over them into appropriate codes for animating the cathodes in cochlea of ear. The cathode actuates sound-related nerve filaments to give hearing sensation. The expense of the CI alone goes to around 100,000 US dollars. For the efficient less well-to-do individuals with hearing sickness, it might be too exorbitant to even consider affording for this hardware to recoup from the conference misfortune. It gets important to cut down the expense. The cost decrease might be accomplished with diminished region, low force and rapid activity of the CI. This goal intuited both the simple and the computerized based CI originators to inquire about their techniques to give individuals less expensive and profoundly understandable CI. The primary objective of this paper is to develop reconfigurable DSP architectures for the filter banks in speech processor of CI with the following features like minimized area of the filter, reduced power consumption of the speech processor and enhanced presentation of the filter. This paper involves the design and hardware implementation of narrow band pass FIR filter for speech processor of CI using the Xilinx System Generator (XSG) tool on Virtex 7 FPGA.

Towards a performance-aware power capping orchestrator for the Xen hypervisor

In the last few years, multi-core processors entered into the domain of embedded systems: this, together with virtualization techniques, allows multiple applications to easily run on the same System-on-Chip (SoC). As power consumption remains one of the most impacting costs on any digital system, several approaches have been explored in literature to cope with power caps, trying to maximize the performance of the hosted applications. In this paper, we present some preliminary results and opportunities towards a performance-aware power capping orchestrator for the Xen hypervisor. The proposed solution, called XeMPUPiL, uses the Intel Running Average Power Limit (RAPL) hardware interface to set a strict limit on the processor's power consumption, while a software-level Observe-Decide-Act (ODA) loop performs an exploration of the available resource allocations to find the most power efficient one for the running workload. We show how XeMPUPiL is able to achieve higher performance under different power caps for almost all the different classes of benchmarks analyzed (e.g., CPU-, memory-and IO-bound).

DEP+BURST: Online DVFS Performance Prediction for Energy-Efficient Managed Language Execution

Making modern computer systems energy-efficient is of paramount importance. Dynamic Voltage and Frequency Scaling (DVFS) is widely used to manage the energy and power consumption in modern processors; however, for DVFS to be effective, we need the ability to accurately predict the performance impact of scaling a processor's voltage and frequency. No accurate performance predictors exist for multithreaded applications, let alone managed language applications. In this work, we propose DEP+BURST, a new performance predictor for managed multithreaded applications that takes into account synchronization, interthread dependencies, and store bursts, which frequently occur in managed language workloads. Our predictor lowers the performance estimation error from 27 percent for a state-of-the-art predictor to 6 percent on average, for a set of multithreaded Java applications when the frequency is scaled from 1 to 4 GHz. We also novelly propose an energy management framework that uses DEP+BURST to reduce energy consumption. We first target reducing the processor's energy consumption by lowering its frequency and hence its power consumption, while staying within a user-specified maximum slowdown threshold. For a slowdown of 5 and 10 percent, our energy manager reduces on average 13 and 19 percent of energy consumed by the memory-intensive benchmarks. We then use the energy manager to optimize total system energy, achieving an average reduction of 15.6 percent for a set of Java benchmarks. Accurate performance predictors are key to achieving high performance while keeping energy consumption low for managed language applications using DVFS.

Design and Implementation of FPGA Based Digital Base Band Processor for RFID Reader

RFID ipso facto deals with identification of objects through radio waves. Its use started during World War II in the identification of “Friend-or-Foe” for targets used by the military, such as aircraft and forces. It was only in 1990s, that large scale use of RFID started. The objective of this paper is to implement the digital baseband processor for UHF RFID reader compatible with EPC Global C1G2 /ISO 18000-6 C protocol. The functional simulation of digital base band processor is done using Modelsim simulator. It is verified and tested successfully on FPGA Spartan-6 prototype board for its logic function. A new bit stream encoding and decoding module are presented for the digital base band processor. The synthesis results proved, that the power consumption of the digital base band processor is about 5mW and the number of slice registers and LUTs used are 32 and 33 respectively. The results presented in this paper are better than literature reported in terms of power. Areas of use RFID were supply management, for tracking articles, inventory and also for identification of animals.

3D network-on-chip design for embedded ubiquitous computing systems

A novel 3D NoC topology for embedded ubiquitous computing is proposed.A minimal routing algorithm with path diversity in the 3D NoC Topology is used.A power efficient architecture design for NoC-based embedded ubiquitous computing is introduced. Ubiquitous High-Performance Computing applications, such as cyber-physical systems, sensor networks and virtual reality require the support of terascale embedded systems that can deliver higher performance than current systems. Multi-cores, many-cores and heterogeneous processors are becoming the typical design choices to satisfy these requirements. Inter core communication has been one of the major challenges as it affects the bandwidth and power consumption of the multi-cores processors. Network-on-Chips (NoCs) present a fast and scalable interconnection solution to fulfill the requirements of Ubiquitous High-Performance Computing applications. This paper proposes a novel 3D Network-on-Chip called Octagon for Ubiquitous Computing (OUC) that is designed for Embedded Ubiquitous Computing Systems. OUC provides low network diameter and path diversity. Simulation results show that the proposed topology achieves a significant decrease in latency and an average 21.54% and 12.89% improvement in average throughput under hotspot and uniform traffic pattern respectively.

Energy-efficient heterogeneous resource management for wireless monitoring systems

Abstract Various energy-saving designs have been proposed for reducing the power consumption of processors through dynamic voltage and frequency scaling (DVFS). When dynamic random access memory (DRAM) or peripheral power consumption is high, dynamic power management (DPM) can be adopted to dynamically activate or deactivate devices or to switch them into energy-saving states during idle periods. This paper proposes a heterogeneous resource management mechanism to manage device scheduling for multiple tasks and task scheduling in a processor. A wireless network monitoring system was analyzed as a case study, wherein a resource sharing mechanism was developed for managing the scheduling of multiple wireless adapters, and the concept of instantaneous utilization was leveraged to enable chain-based task scheduling. This paper explores DVFS and DPM energy saving techniques for peripherals and a processor by considering both the required device time and processor time for each task without violating performance requirements under constraints of buffer size. The proposed algorithms were then implemented on a wireless network monitoring system and real traces were collected from a laboratory and downloaded from the UMass Trace Repository for use as inputs. A series of experiments was conducted to evaluate the quality of our algorithms for energy saving within the constraints of system performance requirements and hardware resources.

Adaptive Interplay of DVS and DPM for Power Consumption Reduction in Real-Time Embedded Processors

Objectives: Processors are computing elements of most of the embedded systems. As the technology is growing day by day, processors that are released in the market are mostly embedded processors. Processors are designed to perform concurrent operations and execution at a higher clock rate to meet the performance demands result in large heat dissipation and energy consumption. Thus there is an emphasis on power and energy consumption reduction in real time embedded processors. This work targets to reduce the processor power consumption without violating the real time constraints. Method: In this work, a dynamic power management technique named dynamic counters is employed in real-time system to minimize power consumption. The proposed method facilitates bounding of the events conservatively for effective bounding of future workload. It also employs scheduling ON and OFF time of the devices based on workload bounding at run-time. Simulation analysis is carried out to confirm the performance enhancement of the proposed method. Findings: Energy consumed by the processor increases with the number of event arrivals and switching of modes facilitates significant energy savings. Improvement: Run-time and memory overheads are overcome by dynamic counter technique. Effective bounding of future workload enhances computational efficiency.

The shift from processor power consumption to performance variations: fundamental implications at scale

The Intel Haswell-EP processor generation introduces several major advancements of power control and energy-efficiency features. For computationally intense applications using advanced vector extension (AVX) instructions, the processor cannot continuously operate at full speed but instead reduces its frequency below the nominal frequency to maintain operations within thermal design power (TDP) limitations. Moreover, the running average power limitation (RAPL) mechanism to enforce the TDP limitation has changed from a modeling to a measurement approach. The combination of these two novelties have significant implications. Through measurements on an Intel Sandy Bridge-EP cluster, we show that previous generations have sustained homogeneous performance across multiple CPUs and compensated for hardware manufacturing variability through varying power consumption. In contrast, our measurements on a Petaflop Haswell system show that this generation exhibits rather homogeneous power consumption limited by the TDP and capped by the improved RAPL while providing inhomogeneous performance under full load. Since all of these controls are transparent to the user, this behavior is likely to complicate performance analysis tasks and impact tightly coupled parallel applications.

Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage

Scaling supply voltage to values near the threshold voltage allows a dramatic decrease in the power consumption of processors; however, the lower the voltage, the higher the sensitivity to process variation, and, hence, the lower the reliability. Large SRAM structures, like the last-level cache (LLC), are extremely vulnerable to process variation because they are aggressively sized to satisfy high density requirements. In this paper, we propose Concertina, an LLC designed to enable reliable operation at low voltages with conventional SRAM cells. Based on the observation that for many applications the LLC contains large amounts of null data, Concertina compresses cache blocks in order that they can be allocated to cache entries with faulty cells, enabling use of 100 percent of the LLC capacity. To distribute blocks among cache entries, Concertina implements a compression- and fault-aware insertion/replacement policy that reduces the LLC miss rate. Concertina reaches the performance of an ideal system implementing an LLC that does not suffer from parameter variation with a modest storage overhead. Specifically, performance degrades by less than 2 percent, even when using small SRAM cells, which implies over 90 percent of cache entries having defective cells, and this represents a notable improvement on previously proposed techniques.

Design and Development of an RF Energy Harvesting Wireless Sensor Node (EH-WSN) for Aerospace Applications

Numerous applications of wireless sensor networks are constrained by the limited battery power of the sensors. The power consumption of processors and microcontrollers could be scaled down dramatically with the new advances in microelectronics. This reduction gives rise to the possibility of energy harvesting sources to power wireless sensor nodes. In this paper a summary is given of our ongoing research work on RF Energy Harvesting Wireless Sensor Node (EH-WSN) which can plug-in to the already developed Wireless Instrumentation System (WIS) for aerospace applications. Present WSN's which are powered from battery have limited operational lifetime. While energy harvesting has the potential to enable near-perpetual system operation, design of which is a complex trade-off due to the interaction of numerous factors such as the characteristics of the energy source, power supply requirements, power management futures, WSN application behaviour, chemistry and capacity of batteries used etc. In this work, we have identified a suitable power harvesting cum battery management scheme which harvests power consistently and deterministically from a secondary RF source which can be used even in harsh real-time applications. Using a RF power harvesting receiver IC and a compact power management cum storage circuit, we establish the test bed and conduct a series of experiments to verify the effectiveness of the proposed scheme. We have demonstrated continuous operation of the sensor node at an operating distance of 2 meters from the RF power source for a data rate of 240 sps. This is achieved by using special synchronized MAC protocol, low power techniques, usage of low leakage components and systematic coding of the micro controller firmware. This paper provides an insight into how various power reduction techniques can be used and orchestrated such that satisfactory performance can be achieved for a given energy budget.

A low power non-volatile LR-WPAN baseband processor with wake-up identification receiver

The paper proposes a low power non-volatile baseband processor with wake-up identification (WUI) receiver for LR-WPAN transceiver. It consists of WUI receiver, main receiver, transmitter, non-volatile memory (NVM) and power management module. The main receiver adopts a unified simplified synchronization method and channel codec with proactive Reed-Solomon Bypass technique, which increases the robustness and energy efficiency of receiver. The WUI receiver specifies the communication node and wakes up the transceiver to reduce average power consumption of the transceiver. The embedded NVM can backup/restore the states information of processor that avoids the loss of the state information caused by power failure and reduces the unnecessary power of repetitive computation when the processor is waked up from power down mode. The baseband processor is designed and verified on a FPGA board. The simulated power consumption of processor is 5.1μW for transmitting and 28.2μW for receiving. The WUI receiver technique reduces the average power consumption of transceiver remarkably. If the transceiver operates 30 seconds in every 15 minutes, the average power consumption of the transceiver can be reduced by two orders of magnitude. The NVM avoids the loss of the state information caused by power failure and energy waste caused by repetitive computation.

Thermal analysis of stochastic DVFS-enabled multicore real-time systems

This paper considers a multicore system, equipped with dynamic voltage/frequency scaling (DVFS), which runs real-time jobs with probabilistic characteristics. The DVFS policy directly affects the performance of this system as well as its power consumption through impacting both dynamic and leakage powers. While power consumption determines the processor thermal behavior, the temperature in turn affects the processor power consumption by impacting the leakage power. Additionally, temperature variation of a core is coupled with the thermal behaviors of the other cores, namely thermal effects of the surrounding components. These inter-effects make sophisticated relations between the nature of the stochastic real-time system and its performance, power consumption, and temperature behavior. In this paper, we first present an exact thermal analysis approach for the specified system considering these inter-effects. We then propose a scalable approximate method for thermal analysis of the system based on the exact analysis. The proposed analytical method outperforms the traditional simulation-based methods in terms of time complexity, by approximately three orders of magnitude, while introducing a relative error of less than 0.8 % for the mentioned setups. Also, we show the efficacy of the proposed analytical method in temperature-aware power minimization, resulting in significant reductions in the system-wide power consumption.

A 130.3 mW 16-Core Mobile GPU With Power-Aware Pixel Approximation Techniques

Intensive pixel shading dominates the power dissipation of the graphics pipeline as the screen resolution grows. In this work, we propose a 130.3 mW 16-core mobile GPU with three pixel approximation techniques and a corresponding tile-based rasterization architecture. The proposed architecture can trade-off between power consumption and visual quality to provide power-aware capability, and is fabricated with TSMC 45 nm technology. The feasibility and effectiveness of these techniques are verified in this chip prototype. The implementation results show that, with satisfactory visual quality, 52.32% of the power consumption of the shader processors can be empirically reduced with an experimental Approximated Precision Shader architecture and a Screen-space Approximated Lighting technique. Furthermore, the Approximated Texturing technique can reduce 24.57% of L1 cache updates in our evaluation.

On-Line Dynamic Voltage Scaling for EDZL Scheduling on Symmetric Multiprocessor Real-Time Systems

EDZL (Earliest Deadline Zero Laxity) scheduling is known to be at least as EDF (Earliest Deadline First) in task scheduling on symmetric multiprocessor real-time systems; however, there are few works on energy conversation on the EDZL. This paper proposes an on-line Dynamic Voltage Scaling (DVS) algorithm of the global EDZL to reduce energy consumption of real-time tasks. The proposed algorithm dynamically adjusts processor speed at each scheduling point with re-assigning deadlines of active jobs that reduces power consumption of processors while making all real-time tasks schedulable by EDZL. Extensive simulations show that the proposed algorithm reduces power consumption more than the previous algorithm for EDZL.