Processing Power Consumption Research Articles

Improving Cache Power and Performance Using Deterministic Naps and Early Miss Detection

Cache memory systems consume a significant portion of static and dynamic power consumption in processors. Similarly, the access latency through the cache memory system significantly impacts the overall processor performance. Several techniques have been proposed to tackle the individual power or performance. However, almost all trade off performance for power or vice versa. We propose a novel scheme that improves performance while reducing both static and dynamic power with minimal area overhead. Our proposed scheme reduces dynamic power by using a hash-based mechanism to minimize the number of cache lines read during program execution. This is achieved by identifying and not reading those that are guaranteed non-matches (i.e., cache misses) to a new access. Performance improvement occurs when all cache lines of a referenced set are determined non-matches to the requested address, and therefore skip a few cache pipe stages as guaranteed misses. Static power savings is achieved by exploiting in-flight cache access information to deterministically lower the power state of cache lines that are guaranteed not to be accessed in the immediate future. These techniques easily integrate into existing cache architectures and were evaluated using widely known CAD tools and benchmarks. We have observed up to 92, 17, and 2 percent improvements in performance, static, and dynamic power, respectively, with less than 3 percent area overhead.

A Stochastic Model for Estimating the Power Consumption of a Processor

Quantitatively estimating the relationship between the workload and the corresponding power consumption of a multicore processor is an essential step towards achieving energy proportional computing. Most existing and proposed approaches use Performance Monitoring Counters (Hardware Monitoring Counters) for this task. In this paper we propose a complementary approach that employs the statistics of CPU utilization (workload) only. Hence, we model the workload and the power consumption of a multicore processor as random variables and exploit the monotonicity property of their distribution functions to establish a quantitative relationship between the random variables. We will show that for a single-core processor the relationship is best approximated by a quadratic function whereas for a dualcore processor, the relationship is best approximated by a linear function. We will demonstrate the plausibility of our approach by estimating the power consumption of both custom-made and standard benchmarks (namely, the SPEC power benchmark and the Apache benchmarking tool) for an Intel and AMD processors.

Runtime power-aware energy-saving scheme for parallel applications

Energy consumption has become a major design constraint in modern computing systems. With the advent of petaflops architectures, power-efficient software stacks have become imperative for scalability. Modern processors provide techniques, such as dynamic voltage and frequency scaling (DVFS), to improve energy efficiency on-the-fly. Without careful application, however, DVFS and throttling may cause significant performance loss due to the system overhead. Typically, these techniques are used by constraining a priori the application performance loss, under which the energy savings are sought. This paper discusses potential drawbacks of such usage and proposes an energy-saving scheme that takes into account the instantaneous processor power consumption as presented by the 'running average power limit' (RAPL) technology from Intel. Thus, the need for the user to predefine a performance loss tolerance is avoided. Experiments, performed on NAS parallel benchmarks and large-scale linear system solvers from the pARMS package, show that the proposed scheme saves more energy than the approaches based on the predefined performance loss.

An adaptive digital processor for power efficiency enhancement in hybrid supply modulators

SummaryA novel digital envelope modulator for envelope tracking radio frequency power amplifier is presented in this paper. The proposed modulator consists of a parallel combination of linear class AB and switching class D power amplifiers that are controlled digitally. In the previous analog architectures, the requirements needed for the AB operational amplifier such as high‐current driving capability, high bandwidth and large output swing is usually obtainable at high overall static power dissipation. The digitally controlled power opamp presented here not only provides the aforementioned requirements but also reduces power dissipation compared with previous work. Furthermore, the digital control of the modulator makes it adaptive to the input signal variations in comparison with conventional analog parallel hybrid envelope modulators. The digital processor of the modulator is evaluated with a 45‐nm complementary metal oxide semiconductor technology. The overall power consumption of the digital processor is around 142 mW at 1.5‐GHz clock frequency. As an application, the designed digital class AB is incorporated in a complete envelope modulator architecture. The overall efficiency of the modulator, including the digital processor power consumption, is around 82% at an average 32 dBm output power for a 5‐MHz input signal. Copyright © 2015 John Wiley & Sons, Ltd.

New Thermal-Aware Voltage Island Formation for 3D Many-Core Processors

The power consumption of 3D many-core processors can be reduced, and the power delivery of such processors can be improved by introducing voltage island (VI) design using on-chip voltage regulators. With the dramatic growth in the number of cores that are integrated in a processor, however, it is infeasible to adopt per-core VI design. We propose a 3D many-core processor architecture that consists of multiple voltage clusters, where each has a set of cores that share an on-chip voltage regulator. Based on the architecture, the steady state temperature is analyzed so that the thermal characteristic of each voltage cluster is known. In the voltage scaling and task scheduling stages, the thermal characteristics and communication between cores is considered. The consideration of the thermal characteristics enables the proposed VI formation to reduce the total energy consumption, peak temperature, and temperature gradients in 3D many-core processors.

Flexible Prime-Field Genus 2 Hyperelliptic Curve Cryptography Processor with Low Power Consumption and Uniform Power Draw

This paper presents an energy -efficient (low power) prime-field hyperelliptic -curve cryptography (HECC) processor with uniform power draw. The HECC processor performs divisor scalar multiplication on the Jacobian of genus 2 hyperelliptic curves defined over prime fields for arbitrary field and curve parameters. It supports the most frequent case of divisor doubling and addition. The optimized implementation, which is synthesized in a 0.13 mm standard CMOS technology, performs an 81 -bit divisor multiplication in 503 ms consuming only 6.55 mJ of energy (average pow er consumption is 12.76 mW.) We also present a technique to make the power consumption of the HECC processor more uniform and lower the peaks of its power consumption .

Quality of Service-Aware Dynamic Voltage and Frequency Scaling for Embedded GPUs

Dynamic voltage and frequency scaling (DVFS) is a key technique for reducing processor power consumption in mobile devices. In recent years, mobile system-on-chips (SoCs) has supported DVFS for embedded graphics processing units (GPUs) as the processing power of embedded GPUs has been increasing steadlily. The major challenge of applying DVFS to a processing unit is to meet the quality of service (QoS) requirement while achieving a reasonable power reduction. In the case of GPUs, the QoS requirement can be specified as the frame-per-second (FPS) which the target GPU should achieve. The proposed DVFS technique ensures a consistent GPU performance by scaling the operating clock frequency in a way that it maintains a uniform FPS.

Time and Energy Efficient DVS Scheduling for Real-Time Pinwheel Tasks

Dynamic voltage/frequency scaling (DVFS) is one of the most effective techniques for reducing energy use. In thispaper, we focus on the pinwheel task model to develop a variable voltage processor with d discrete voltage/speedlevels. Depending on the granularity of execution unit to which voltage scaling is applied, DVFS scheduling can bedefined in two categories: (i) inter-task DVFS and (ii) intra-task DVFS. In the periodic pinwheel task model, wemodified the definitions of both intra- and inter-task and design their DVFS scheduling to reduce the powerconsumption of DVFS processors. Many previous approaches have solved DVFS problems by generating a canonicalschedule in advance and thus require pseudo polynomial time and space because the length of a canonical scheduledepends on the hyperperiod of the task periods and is generally of exponential length. To limit the length of thecanonical schedules and predict their task execution, tasks with arbitrary periods are first transformed into harmonicperiods and their key features are profiled. The proposed methods have polynomial time and space complexities, andexperimental results show that, under identical assumptions, the proposed methods achieve more energy savingsthan the previous methods.

STEAM

Recent empirical studies have shown that multicore scaling is fast becoming power limited, and consequently, an increasing fraction of a multicore processor has to be under clocked or powered off. Therefore, in addition to fundamental innovations in architecture, compilers and parallelization of application programs, there is a need to develop practical and effective dynamic energy management (DEM) techniques for multicore processors. Existing DEM techniques mainly target reducing processor power consumption and temperature, and only few of them have addressed improving energy efficiency for multicore systems. With energy efficiency taking a center stage in all aspects of computing, the focus of the DEM needs to be on finding practical methods to maximize processor efficiency. Towards this, this article presents STEAM -- an optimal closed-loop DEM controller designed for multicore processors. The objective is to maximize energy efficiency by dynamic voltage and frequency scaling (DVFS). Energy efficiency is defined as the ratio of performance to power consumption or performance-per-watt (PPW). This is the same as the number of instructions executed per Joule. The PPW metric is actually replaced by P α PW (performance α -per-Watt), which allows for controlling the importance of performance versus power consumption by varying α. The proposed controller was implemented on a Linux system and tested with the Intel Sandy Bridge processor. There are three power management schemes called governors , available with Intel platforms. They are referred to as (1) Powersave (lowest power consumption), (2) Performance (achieves highest performance), and (3) Ondemand . Our simple and lightweight controller when executing SPEC CPU2006, PARSEC, and MiBench benchmarks have achieved an average of 18% improvement in energy efficiency (MIPS/Watt) over these ACPI policies. Moreover, STEAM also demonstrated an excellent prediction of core temperatures and power consumption, and the ability to control the core temperatures within 3 ˆ C of the specified maximum. Finally, the overhead of the STEAM implementation (in terms of CPU resources) is less than 0.25%. The entire implementation is self-contained and can be installed on any processor with very little prior knowledge of the processor.

Code Density and Energy Efficiency of Exposed Datapath Architectures

Exposing details of the processor datapath to the programmer is motivated by improvements in the energy efficiency and the simplification of the microarchitecture. However, an instruction format that can control the data path in a more explicit manner requires more expressiveness when compared to an instruction format that implements more of the control logic in the processor hardware and presents conventional general purpose register based instructions to the programmer. That is, programs for exposed datapath processors might require additional instruction memory bits to be fetched, which consumes additional energy. With the interest in energy and power efficiency rising in the past decade, exposed datapath architectures have received renewed attention. Several variations of the additional details to expose to the programmer have been proposed in the academy, and some exposed datapath features have also appeared in commercial architectures. The different variations of proposed exposed datapath architectures and their effects to the energy efficiency, however, have not so far been analyzed in a systematic manner in public. This article provides a review of exposed datapath approaches and highlights their differences. In addition, a set of interesting exposed datapath design choices is evaluated in a closer study. Due to the fact that memories constitute a major component of power consumption in contemporary processors, we analyze instruction encodings for different exposed datapath variations and consider the energy required to fetch the additional instruction bits in comparison to the register file access savings achieved with the exposed datapath.

Low-power wearable respiratory sound sensing.

Building upon the findings from the field of automated recognition of respiratory sound patterns, we propose a wearable wireless sensor implementing on-board respiratory sound acquisition and classification, to enable continuous monitoring of symptoms, such as asthmatic wheezing. Low-power consumption of such a sensor is required in order to achieve long autonomy. Considering that the power consumption of its radio is kept minimal if transmitting only upon (rare) occurrences of wheezing, we focus on optimizing the power consumption of the digital signal processor (DSP). Based on a comprehensive review of asthmatic wheeze detection algorithms, we analyze the computational complexity of common features drawn from short-time Fourier transform (STFT) and decision tree classification. Four algorithms were implemented on a low-power TMS320C5505 DSP. Their classification accuracies were evaluated on a dataset of prerecorded respiratory sounds in two operating scenarios of different detection fidelities. The execution times of all algorithms were measured. The best classification accuracy of over 92%, while occupying only 2.6% of the DSP's processing time, is obtained for the algorithm featuring the time-frequency tracking of shapes of crests originating from wheezing, with spectral features modeled using energy.

A Study on the Use of Performance Counters to Estimate Power in Microprocessors

We present a study on estimating the dynamic power consumption of a processor based on performance counters. Today's processors feature a large number of such counters to monitor various CPU and memory parameters, such as utilization, occupancy, bandwidth, page, cache, and branch buffer hit rates. The use of various sets of performance counters to estimate the power consumed by the processor has been demonstrated in the past. Our goal is to find out whether there exists a subset of counters that can be used to estimate, with sufficient accuracy, the dynamic power consumption of processors with varying microarchitecture. To this end, we consider two recent processor configurations representing two extremes of the performance spectrum, one targeting low power and the other high performance. Our results indicate that only three counters measuring 1) the number of fetched instructions, 2) level-1 cache hits, and 3) dispatch stalls are sufficient to achieve adequate precision. These counters are shown to be effective in predicting the dynamic power consumption across processors of varying resource sizes achieving a prediction accuracy of 95%.

Application-aware adaptive cache architecture for power-sensitive mobile processors

Today, mobile smartphones are expected to be able to run the same complex, algorithm-heavy, memory-intensive applications that were originally designed and coded for general-purpose processors. All the while, it is also expected that these mobile processors be power-conscientious as well as of minimal area impact. These devices pose unique usage demands of ultra-portability but also demand an always-on, continuous data access paradigm. As a result, this dichotomy of continuous execution versus long battery life poses a difficult challenge. This article explores a novel approach to mitigating mobile processor power consumption while abating any significant degradation in execution speed. The concept relies on efficiently leveraging both compile-time and runtime application memory behavior to intelligently target adjustments in the cache to significantly reduce overall processor power, taking into account both the dynamic and leakage power footprint of the cache subsystem. The simulation results show a significant reduction in power consumption of approximately 13% to 29%, while only incurring a nominal increase in execution time and area.

Effects of Using Advanced Cooling Systems on the Overall Power Consumption of Processors

The increase in power dissipation of high-performance computing systems has driven the need for advance cooling systems. Recently, localized spot cooling using embedded thermoelectric coolers (eTECs) and chip-level cooling using miniature-scale refrigeration system have been demonstrated for mitigating thermal and power problems in high-performance computing systems. Operating integrated circuit at a lower temperature can result in reduced electronic power, improved reliability, and potentially improved speed. However, total power dissipation must include both the electronic power and the cooling power to quantify overall system performance. This paper explores the amount of total power reduction using two different types of cooling system for electronic cooling, by using a model that incorporates both a real-world microprocessor and cooling systems. The analysis indicates that an optimal operating point depends on the parameters of electronics and cooling systems. Our results show that cooling the right element (the cache) using eTEC gives a modest 3% improvement but provides the benefit of full integration. On the other hand, chip-level cooling using our refrigeration system results in a total power savings of 25% over the nonrefrigerated design.

Optimizing cache energy efficiency in multicore power system simulations

Due to recent trends in computer chip design and architecture, the power consumption of computing systems is increasing. Further, with increasing number of cores on a single chip, the size of cache is also increasing and hence, their contribution in overall processor power consumption has become significant. As computing systems become ubiquitous, their excessive power consumption is likely to increase the demands of electricity, thus increasing the level of stress on power systems. In this paper, we propose an approach for reducing cache energy consumption in power system dynamic simulations which are computationally intensive. Our approach is based on the observation that there exists large intra- and inter-program variation in cache resource demand in simulation of different contingencies. Thus, using decay cache technique, we dynamically turn off the cache blocks to save cache energy. In multicore systems, the requirements of meeting worst-case cache demand leads to over-provisioning of resources and hence, saving cache energy is even more important in multicore systems. Hence, we evaluate energy savings in the context of both dual-core and quad-core processors. We simulate several contingencies of different power systems using time domain simulation. Further, we explore the opportunity of dynamically saving cache energy by using a computer architecture simulator and simulate dual-core and quad-core processor configurations. The results show that our technique is effective in saving cache energy and also keeps the loss in performance minimal.

Register spilling via transformed interference equations for PAC DSP architecture

SUMMARYDigital signal processors (DSPs) with very long instruction word (VLIW) data‐path architectures are increasingly being deployed on embedded devices for multimedia processing applications. To reduce the power consumption and design cost of VLIW DSP processors, distributed register files and multibank register architectures are being adopted to reduce the number of read and write ports associated with register files, which presents new challenges for devising compiler optimization schemes. This paper addresses the issues of reducing the spill code for a VLIW DSP with distributed register files. Spill code produced by register allocation is traditionally handled by memory spills, but the multibank register‐file architecture provides the opportunity to spill‐out register values onto different register banks. We present a conceptual framework based on the universal and the proxy interference graphs to model the live ranges of registers for spilling codes to different register banks. Heuristic algorithms are then developed on the basis of this concept. By heuristically estimating the register pressure for each register file, we treat different register banks as optional spilling locations in addition to traditional spilling to memory. Experiments were performed on the parallel architecture core VLIW DSP with distributed register files by incorporating our proposed optimization schemes into an Open64‐based compiler. The experimental results show that our approach can improve the performances on average for DSPStone and MiBench benchmarks with spilling cases by 7.1% and 21.6%, respectively, compared with the one always handling spill code in memory. Copyright © 2013 John Wiley & Sons, Ltd.

SRAM standby leakage decoupling analysis for different leakage reduction techniques

SRAM standby leakage reduction plays a pivotal role in minimizing the power consumption of application processors. Generally, four kinds of techniques are often utilized for SRAM standby leakage reduction: Vdd lowering (VDDL), Vss rising (VSSR), BL floating (BLF) and reversing body bias (RBB). In this paper, we comprehensively analyze and compare the reduction effects of these techniques on different kinds of leakage. It is disclosed that the performance of these techniques depends on the leakage composition of the SRAM cell and temperature. This has been verified on a 65 nm SRAM test macro.

Injection Based Dynamic Power Management and a Policy for Multiprocessor Systems

Power consumption has become a critical issue in designing computer systems. Dynamic power management is an approach that aims to reduce power consumption at system level by selectively placing components into low power states. Time-out and prediction based policies are often adopted in practical systems. However, they have to accurately determine the time in low power state and otherwise the saved power consumption is not worth the loss of performance. In this paper, a power management for multiprocessor systems is proposed to optimally reduce the power consumption of multiple processors. The key feature of the proposed power management is that how long to place a processor into low power state is determined in advance but not decided when a processor becomes idle. Thus, many off-time quanta are pre-determined beforehand. The proposed power management schedules the off-time quanta to processors and a processor is placed into low power state if an off-time quantum is assigned to it. It seems that processors execute special tasks which just reduce the power supplied to them. Hence, the off-time quanta are also named sleep tasks, which are virtual and injected into the original task traffic. By doing so, the inaccurate time length of sleep tasks hardly impacts on the performance, because if a processor is blocked by a sleep task there is another one available except that all the others are blocked at the same time. Then a probabilistic policy is also proposed to optimally assign sleep tasks from the waiting queue to the processors for minimum loss of performance. In the proposed policy, high priority is given to real tasks and sleep tasks are serviced only on necessity. The analysis of the probabilistic policy is performed on a queueing model and shows that the policy is asymptotically optimal. The proposed power management and policy are further examined in empirical studies.

Time-based power control architecture for application processors in smartphones

Proposed is an architecture for reducing the power consumption of an application processor (AP) in a smartphone. The proposed architecture is designed for sharing the main memory between the AP and modem blocks. A power-saving algorithm is proposed that focuses on random and sparse data patterns in connected and idle modes. The algorithm automatically performs power/clock gating without the intervention of the CPU, unlike dynamic voltage and frequency scaling. To control power gating, a power consumption model is formulated to solve an optimisation problem. The proposed algorithm is verified with electronic system level simulation based on actual scenarios of a mobile terminal. The results show an improvement in power consumption.

Analyzing the Impact of Joint Optimization of Cell Size, Redundancy, and ECC on Low-Voltage SRAM Array Total Area

The increasing power consumption of processors has made power reduction a first-order priority in processor design. Voltage scaling is one of the most powerful power-reduction techniques introduced to date, but is limited to some minimum voltage <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DDMIN</sub> . Below <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DDMIN</sub> on-chip SRAM cells cannot all operate reliably due to increased process variability with technology scaling. The use of larger SRAM cells, which are less sensitive to process variability, allows a reduction in <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DDMIN</sub> . However, since the large-scale memory structures such as last-level caches (LLCs) often determine the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DDMIN</sub> of processors, these structures cannot afford to use large SRAM cells due to the resulting increase in die area. In this paper we first propose a joint optimization of LLC cell size, the number of redundant cells, and the strength of error-correction coding (ECC) to minimize total SRAM area while meeting yield and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DDMIN</sub> targets. The joint use of redundant cells and ECC enables the use of smaller cell sizes while maintaining design targets. Smaller cell sizes more than make up for the extra cells required by redundancy and ECC. In 32-nm technology our joint approach yields a 27% reduction in total SRAM area (including the extra cells) when targeting 90% yield and 600 mV <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DDMIN</sub> . Second, we demonstrate that the ECC used to repair defective cells can be combined with a simple architectural technique, which can also fix particle-induced soft errors, without increasing ECC strength or processor runtime.