Design Space Exploration of Single-Lane OFDM-Based Serial Links for High-Speed Wireline Communications

Abstract

The 4-level pulse-amplitude modulation (PAM-4) with an analog-digital converter (ADC)-based receiver (RX) has become the most commonly employed modulation for ultra-high-speed serial links with the data rate above 100 Gb/s. To support the data rate of 200 Gb/s, orthogonal frequency division multiplexing (OFDM) has been studied recently as one of the possible modulation schemes in the next-generation serial links. The OFDM can feature high bandwidth efficiency without increasing the equalization complexity, leading to a reduced maximum signal amplitude attenuation and lower required DAC/ADC conversion rates given sufficient DAC/ADC resolutions such that the BER is not primarily limited by the data converters’ resolution. This paper presents system-level modeling results of OFDM-based wireline serial links, with a particular emphasis on the impacts of the fast Fourier transform (FFT) processor’s tap count on the serial link performance. The relationship among the cyclic prefix (CP), FFT tap count, and the link bit-error-rate (BER) are thoroughly explained. The analysis explains that the power consumption of a partially-serial FFT processor improves with a larger kernel FFT size, and simulation results show that the BER performance improves with the FFT size where an optimal CP length exists given the FFT size.