Abstract
In this paper is introduced a low power design technique for developing more reliable, functional, and more cost-effective handheld cellular telephones, portable computers, and peripherals. The portability requirements of handheld computers and other portable devices have placed tremendous pressure on electronic equipment designers, who need to deal with restrictions in the size of electronic units and power consumption. Even though battery technology is continuously improving, including reduced power consumption of processors and displays, extensive and continuous use of network services aggravates these issues. Now the onus is on the research and industrial communities to extend battery life and reduce weight. Equally, research on new techniques and technologies continues, to carefully manage energy consumption in mobile devices, while still providing continuous and fast connections to services and applications. This paper also discusses the novel trends in the developments and advancements in the area of low power Very Large Scale Integration (VLSI) design, dynamic power dissipation static power loss in Complementary Metal Oxide Semiconductor (CMOS), and advanced low power technique. Though low power as a well-established domain that undergone lots of developments from transistor sizing, process shrinkage, voltage scaling, clock gating, etc., to adiabatic logic are elaborated.
Highlights
The power technique is presently emerging as the most critical issue in System-on-Chip (SoC) design
From a chip-engineering perspective, effective energy management for an SoC must be built into the design starting at the architecture stage, low-power techniques need to be employed at every stage of the design, from Register Transfer Level (RTL) to Graphic Data System II (GDSII)
Dynamic power is consumed when electronic transistors are switching from one state to another, namely this power consumption is due to the charging and discharging of output load capacitance of a transistor
Summary
The power technique is presently emerging as the most critical issue in System-on-Chip (SoC) design. The necessity for personal electronic devices that today offer greater functionality and performance at lower costs and smaller sizes have increased rapidly. This market trend is driving the need for efficient SoC designs, where the power arises as one of the biggest problems. To cope with the power challenges, a number of new power saving techniques have been developed that can efficiently target both static and dynamic power loss. The selection of power saving strategy becomes one of the most important challenges for designers This presentation starts by covering basic sources of power consumption in CMOS, including both static and dynamic power loss. Future trends in low power design are discussed as well [1, 4 - 6]
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