Low-Power and Low-Leakage Design Techniques in CMOS Technology

Abstract

The primary goal of developing low power consumption device in this modern era is a real test for every VLSI designer. By the process of control scattering, we can minimize the amount of power consumption and area occupying in the VLSI (Very large-Scale Integration) Chip [1]. Control administration procedures, logical methods are configured for low power circuits and their frameworks. Reducing the amount of power consumption, Leakage power in battery-powered and portable devices in VLSI systems has become an important aspect. The reduction of power consumption in any circuit depends on the amount of leakage of transistors. Insights demonstrate that 40% of total power wasted in the form of leakage. This percentage may increase by the process of transistor scaling. Transistor scaling is a method that is used to increase the density of the transistors for the manufacturing of any chip. This paper explores mainly the power-optimization/Leakage of the circuit and its improvement. To minimize the amount of power dissipation and leakage power, the designer should draw attention to the techniques involved. Simulation results has been observed in the SPICE-tool of 35nm Technology.