Low Power Design of High Speed Communication System Using IO Standard Technique over 28 nm VLSI Chip

Abstract

The low power design of Very Large Scale Integration (VLSI) system is one of the hot topic in research. In this chapter, the low power design for VLSI based high-speed communication is realized over 28 nm VLSI chip packed in UltraScale Field Programming Gate Array (FPGA) using proposed technique. The high-speed communication system is taken as case study for the low power design of VLSI system. Similarly, various VLSI design system can be realized to achieve the low power VLSI system design goal. High-speed communication systems provide the smooth operation for global internet traffic and requires high power devices and components.IO standard is powerful interface tool that provides low power consumption using the fast signal termination by mean of electrical characteristics. In result for this work, more than 96% power reduction is achieved for VLSI based high-speed communication system, when operated at 500 GHZ, 900 GHz, 10 THz and 17 THz carrier frequencies using the High-Speed Unterminated Logic IO Standard. The power analysis is performed using XPA analyzer in Xilinx suite.